Accessing the configuration clock

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This FPGA Project was completed in July 2014.

The Spartan 6 FPGA has an internal RC oscillator that is used during the device's initial configuration.

Here's how you can access that clock in your own designs.

   port map (
      CFGCLK    => open,         -- 1-bit output: Configuration logic main clock output.
      CFGMCLK   => config_clock, -- 1-bit output: Configuration internal oscillator clock output.
      EOS       => open,         -- 1-bit output: Active high output signal indicates the End Of Configuration.
      CLK       => '0',          -- 1-bit input: User startup-clock input
      GSR       => '0',          -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
      GTS       => '0',          -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
      KEYCLEARB => '0'           -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)

Depending on your bitstream's configuration settings the clock could be between 1 MHz and 50MHz. Being an RC oscillator it isn't very precise - +/- 50% tolerance, and is very temperature sensitive.

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