Async VGA

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After a bit of thinking, this FPGA Project was completed in an hour in January 2013.

Whem working with modern (eg SDRAM) providing pixels to a VGA subsystem is a awkward, as the memory system only works efficiently if you read bursts, but the VGA subsystem wants a nice smooth stream of pixels. The obvious answer is to put a FIFO between the two, to smooth things out.

I've taken it one step further. All you need to do is put a '1' in the MSB of the fifo data on the first pixel of the frame, and the display subsystem handles switching to an appropriate pixel clock & timing by reprogramming the clock generator.

Verified on the Papilio Plus (Spartan 6 LX9.

Contents

Crossing clock domains

Andrea Venturi asked me what is the purpose of "desired_mode_valid". It is a crufty way to avoid a clock domain crossing issue.

If a desired_mode_valid MSB is '1', then desired_mode_valid is assured to be 100% stable with respect to the the 32MHz clock So when a mode change is needed, here is what is going on in the clk_vga domain (if it is clocking at 75MHz)

T = 0 The need to change resolution is detected
desired_mode_valid is set to "0000",
T = 13.5ns desired_mode_valid is set to "0001"
desired_mode is set to new value
(at this point the VGA section has performed it's part of the mode change T = 27.0ns desired_mode_valid is set to "0011"
T = 50.5ns desired_mode_valid is set to "0111"
T = 54.0 ns. desired_mode_valid is set to "0111"
T = 67.0 ns desired_mode_valid is set to "1111"

Now that the MSB of desired_mode_valid is '1', desired_mode will be stable with respect to the slower 32MHz system clock. The "desired_mode_valid(desired_mode_valid'length-1) = '1' and desired_mode /= current_mode" test will be true and the 32MHz domain will reprogram the DCM_CLKGEN. No motter what the relative phase of the two clocks it is impossible for miscommunication to occur

Source files

Missing from this is the source of the FIFO "vga_fifo". It is a 9-bit wide, 1024 word deep fifo, with a programmable full. You will need ot generate one in the IP Wizard.

The setting for the programmable full depends on latency and burst size of the memory feeding it. If in doubt, use something like 512.

async_vga.vhd

-----------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
-- Name:     asyc_vga
-----------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity async_vga is
    Port ( clk   : in  STD_LOGIC;
           sw    : in   STD_LOGIC_VECTOR(3 downto 0);
           hsync : out STD_LOGIC;
           vsync : out STD_LOGIC;
           red   : out STD_LOGIC_VECTOR (3 downto 0);
           green : out STD_LOGIC_VECTOR (3 downto 0);
           blue  : out STD_LOGIC_VECTOR (3 downto 0));
end async_vga;

architecture Behavioral of async_vga is
   COMPONENT testpattern
   PORT(
      clk         : IN std_logic;          
      sw          : in   STD_LOGIC_VECTOR(3 downto 0);
      fifo_low    : IN std_logic;
      fifo_data   : OUT std_logic_vector(8 downto 0);
      fifo_wr     : OUT std_logic;
      fifo_wr_clk : OUT std_logic
      );
   END COMPONENT;
   
   COMPONENT autoswitch_vga
   PORT(
      clk : IN std_logic;
      fifo_data : IN std_logic_vector(8 downto 0);
      fifo_wr : IN std_logic;          
      fifo_low  : out STD_LOGIC;
      fifo_wr_clk: IN std_logic;
      hSync : OUT std_logic;
      vSync : OUT std_logic;
      red : OUT std_logic_vector(2 downto 0);
      green : OUT std_logic_vector(2 downto 0);
      blue : OUT std_logic_vector(1 downto 0)
      );
   END COMPONENT;

   signal fifo_data    : STD_LOGIC_VECTOR(8 downto 0);
   signal fifo_wr      : STD_LOGIC;
   signal fifo_low     : STD_LOGIC := '1';
   signal clk_buffered : STD_LOGIC;
   signal fifo_wr_clk  : STD_LOGIC;
   
   signal int_red   : STD_LOGIC_VECTOR(2 downto 0);
   signal int_green : STD_LOGIC_VECTOR(2 downto 0);
   signal int_blue  : STD_LOGIC_VECTOR(1 downto 0);
begin 
   red   <= int_red   & int_red(2);
   green <= int_green & int_green(2);
   blue  <= int_blue  & int_blue;

   BUFG_inst : BUFG
   port map (
      O => clk_buffered, -- 1-bit output: Clock buffer output
      I => clk  -- 1-bit input: Clock buffer input
   );
   
   Inst_autoswitch_vga: autoswitch_vga PORT MAP(
      clk       => clk_buffered,
      fifo_data => fifo_data,
      fifo_wr   => fifo_wr,
      fifo_wr_clk   => fifo_wr_clk,
      fifo_low  => fifo_low,
      hSync     => hSync,
      vSync     => vSync,
      red       => int_red,
      green     => int_green,
      blue      => int_blue
   );

   Inst_testpattern: testpattern PORT MAP(
      clk       => clk_buffered,
      sw           => sw,
      fifo_low  => fifo_low,
      fifo_data => fifo_data,
      fifo_wr   => fifo_wr,
      fifo_wr_clk => fifo_wr_clk
   );
end Behavioral;

autoswitch_vga.vhd

----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
-- 
-- Description: A multi-mode VGA output module that can generate 
-- 640x480, 800x600m 1024x768 or 1280x720 based on bytes in a FIFO
--
-- The low eight bits of the data in the fifo is RGB (332), the MSB is a flag to
-- indicate if this is the first byte of the frame.
--
-- THE CONSTANTS USED TO REPROGRAM THE DCM_CLKGEN ARE BASED ON A 32MHz SIGNAL FOR 
-- CLK. IF USING A DIFFERENT CLOCK YOU WILL NEED TO CHANGE THEM!
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

library UNISIM;
use UNISIM.VComponents.all;


entity autoswitch_vga is
    Port ( clk       : in  STD_LOGIC;
           fifo_data : in  STD_LOGIC_VECTOR (8 downto 0);
           fifo_wr   : in  STD_LOGIC;
           fifo_wr_clk  : in  STD_LOGIC;
           fifo_low  : out STD_LOGIC;
           hSync     : out STD_LOGIC;
           vSync     : out STD_LOGIC;
           red       : out STD_LOGIC_VECTOR (2 downto 0);
           green     : out STD_LOGIC_VECTOR (2 downto 0);
           blue      : out STD_LOGIC_VECTOR (1 downto 0));
end autoswitch_vga;

architecture Behavioral of autoswitch_vga is
   COMPONENT vga_fifo
   PORT (
      wr_clk    : IN STD_LOGIC;
      rd_clk    : IN STD_LOGIC;
      din       : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
      wr_en     : IN STD_LOGIC;
      rd_en     : IN STD_LOGIC;
      dout      : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
      full      : OUT STD_LOGIC;
      empty     : OUT STD_LOGIC;
      prog_full : OUT STD_LOGIC
   );
   END COMPONENT;

   constant MODE_INVALID  : std_logic_vector(3 downto 0) := "0000";
   constant MODE_640x480  : std_logic_vector(3 downto 0) := "0001";
   constant MODE_800x600  : std_logic_vector(3 downto 0) := "0010";
   constant MODE_1024x768 : std_logic_vector(3 downto 0) := "0100";
   constant MODE_1280x720 : std_logic_vector(3 downto 0) := "1000";

   signal  desired_mode: std_logic_vector(3 downto 0) := MODE_800x600;
   signal  current_mode: std_logic_vector(3 downto 0) := MODE_INVALID;

   signal clk_vga      : std_logic;
   signal prog_data    : std_logic;
   signal prog_en      : std_logic;
   signal fifoRead     : std_logic := '0';
   signal fifo_pfull   : std_logic := '0';
   signal prog_data_sr : std_logic_vector(27 downto 0) := (others => '0');
   signal prog_en_sr   : std_logic_vector(27 downto 0) := (others => '0');

   signal hcounter   : unsigned(10 downto 0) := (others => '0');
   signal vcounter   : unsigned(10 downto 0) := (others => '0');
   
   signal hVisible    : unsigned(10 downto 0);
   signal hStartSync  : unsigned(10 downto 0);
   signal hEndSync    : unsigned(10 downto 0);
   signal hMax        : unsigned(10 downto 0);
   signal hSyncActive : std_logic := '1';
   constant ZERO       : unsigned(10 downto 0) := (others => '0');
   
   signal vVisible    : unsigned(10 downto 0);
   signal vStartSync  : unsigned(10 downto 0);
   signal vEndSync    : unsigned(10 downto 0);
   signal vMax        : unsigned(10 downto 0);
   signal vSyncActive : std_logic := '1';
   
   signal hSyncNext : std_logic := '0';
   signal vSyncNext : std_logic := '0';

   signal framePixels : unsigned(21 downto 0) := (others => '0');
   signal pixelsPerFrame : unsigned(21 downto 0) := (others => '0');

   signal fifo_read_data : STD_LOGIC_VECTOR (8 downto 0);
   signal desired_mode_valid : STD_LOGIC_VECTOR (3 downto 0);
begin
   prog_data <= prog_data_sr(0);
   prog_en   <= prog_en_sr(0);
   
process(clk)
   begin
      if rising_edge(clk) then
         -- Update the clock reprogramming signals
         prog_en_sr   <= '0' & prog_en_sr((prog_en_sr'length)-1 downto 1);
         prog_data_sr <= '0' & prog_data_sr((prog_data_sr'length)-1 downto 1);
         
         -- Do we need to switch modes? 
         if desired_mode_valid(desired_mode_valid'length-1) = '1' and desired_mode /= current_mode and unsigned(prog_en_sr) = 0 then
            case desired_mode is 
            when MODE_640x480  =>
               -- switch to 25MHz
               prog_en_sr   <= "1000" & "11111111" & "11" & "0000" & "11111111" & "11"; -- Two 10-bit xfers + 1-bit 'go'
               prog_data_sr <= "0000" & "00001010" & "11" & "0000" & "00001101" & "01"; -- Code for D 14 M 11
               current_mode <= desired_mode;

               hVisible    <= ZERO + 640; 
               hStartSync  <= ZERO + 640+16;
               hEndSync    <= ZERO + 640+16+96;
               hMax        <= ZERO + 800-1;
               vSyncActive <= '0';

               vVisible    <= ZERO + 480;
               vStartSync  <= ZERO + 480+10;
               vEndSync    <= ZERO + 480+10+2;
               vMax        <= ZERO + 480+10+2+33-1;
               hSyncActive <= '0';

            when MODE_800x600  =>
               -- switch to 40MHz
               prog_en_sr   <= "1000" & "11111111" & "11" & "0000" & "11111111" & "11"; -- Two x 10-bit xfers + 1-bit 'go'
               prog_data_sr <= "0000" & "00000100" & "11" & "0000" & "00000011" & "01"; -- Code for D 5 M 4
               current_mode <= desired_mode;

               hVisible    <= ZERO + 800;
               hStartSync  <= ZERO + 800+40;
               hEndSync    <= ZERO + 800+40+128;
               hMax        <= ZERO + 800+40+128+88-1;
               vSyncActive <= '1';

               vVisible    <= ZERO + 600;
               vStartSync  <= ZERO + 600+1;
               vEndSync    <= ZERO + 600+1+4;
               vMax        <= ZERO + 600+1+4+23-1;
               hSyncActive <= '1';

            when MODE_1024x768  =>
               -- switch to 64.0MHz - should be 65
               prog_en_sr   <= "1000" & "11111111" & "11" & "0000" & "11111111" & "11"; -- Two x 10-bit xfers + 1-bit 'go'
               prog_data_sr <= "0000" & "00000001" & "11" & "0000" & "00000000" & "01" ; -- Code for D 1 M 2
               current_mode <= desired_mode;

               hVisible    <= ZERO + 1024;
               hStartSync  <= ZERO + 1024+24;
               hEndSync    <= ZERO + 1024+24+136;
               hMax        <= ZERO + 1024+24+136+160-1;
               vSyncActive <= '0';

               vVisible    <= ZERO + 768;
               vStartSync  <= ZERO + 768+3;
               vEndSync    <= ZERO + 768+3+6;
               vMax        <= ZERO + 768+3+6+29-1;
               hSyncActive <= '0';

            when MODE_1280x720  =>
               -- switch to 74.6MHz
               prog_en_sr   <= "1000" & "11111111" & "11" & "0000" & "11111111" & "11"; -- Two x 10-bit xfers + 1-bit 'go'
               prog_data_sr <= "0000" & "00000110" & "11" & "0000" & "00000010" & "01" ; -- Code for D 3 M 7
               current_mode <= desired_mode;

               hVisible    <= ZERO + 1280;
               hStartSync  <= ZERO + 1280+72;
               hEndSync    <= ZERO + 1280+72+80;
               hMax        <= ZERO + 1280+72+80+216-1;
               vSyncActive <= '1';

               vVisible    <= ZERO + 720;
               vStartSync  <= ZERO + 720+3;
               vEndSync    <= ZERO + 720+3+5;
               vMax        <= ZERO + 720+3+5+22-1;
               hSyncActive <= '1';
               
            when others =>
            
            end case;
         end if;
      end if;
   end process;

process(hCounter, vCounter, hVisible, vVisible, fifo_read_data)
   begin
      fifoRead <= '0';
      
      if hCounter = 0 and vCounter = 0 then
         fifoRead <= '1';
      end if;
      
      if fifo_read_data(8) = '0' and hCounter < hVisible and vCounter < vVisible then
         fifoRead <= '1';
      end if;
   end process;
   
process(clk_vga)
   begin
      if rising_edge(clk_vga) then            
         hSync <= hSyncNext;
         vSync <= vSyncNext;
         
         -- Blanking 
         if  hCounter < hVisible and vCounter < vVisible then         
            red   <= fifo_read_data(7 downto 5);
            green <= fifo_read_data(4 downto 2);
            blue  <= fifo_read_data(1 downto 0);
         else
            red   <= (others => '0');
            green <= (others => '0');
            blue  <= (others => '0');
         end if;
         
         -- mode switching
         desired_mode_valid <= desired_mode_valid(desired_mode_valid'length-2 downto 0) & '1';
         case pixelsPerFrame is
            when to_unsigned(640*480, 22) => -- 640x480
               -- Do we need to switch video modes ?
               if  desired_mode /= MODE_640x480 then         
                  if desired_mode_valid(desired_mode_valid'length-1) = '1' then
                     desired_mode_valid <= (others => '0');
                  else
                     desired_mode <= MODE_640x480;
                  end if;
               end if;
            when to_unsigned(800*600, 22) => -- 800x600
               if  desired_mode /= MODE_800x600 then         
                  if desired_mode_valid(desired_mode_valid'length-1) = '1' then
                     desired_mode_valid <= (others => '0');
                  else
                     desired_mode <= MODE_800x600;
                  end if;
               end if;
            when to_unsigned(1024*768, 22) => 
               if  desired_mode /= MODE_1024x768 then         
                  if desired_mode_valid(desired_mode_valid'length-1) = '1' then
                     desired_mode_valid <= (others => '0');
                  else
                     desired_mode <= MODE_1024x768;
                  end if;
               end if;
            when to_unsigned(1280*720, 22) => 
               if  desired_mode /= MODE_1280x720 then         
                  if desired_mode_valid(desired_mode_valid'length-1) = '1' then
                     desired_mode_valid <= (others => '0');
                  else
                     desired_mode <= MODE_1280x720;
                  end if;
               end if;
            when others =>
         end case;
         
         -- Counting the number of pixels in a frame
         if fifoRead = '1' then 
            framePixels <= framePixels + 1;
            if fifo_read_data(8) = '1' then
               pixelsPerFrame <= framePixels+1;
               framePixels <= (others => '0');
            end if;
         end if;

         -- Generate the sync Pulses
         if vcounter = vStartSync then 
            vSyncNext <= vSyncActive;
         elsif vCounter = vEndSync then
            vSyncNext <= not(vSyncActive);
         end if;

         if hcounter = hStartSync then 
            hSyncNext <= hSyncActive;
         elsif hCounter = hEndSync then
            hSyncNext <= not(hSyncActive);
         end if;

         -- Advance the position counters
         IF hCounter = hMax  THEN
           -- starting a new line
           hCounter <= (others => '0');
           IF vCounter = vMax THEN
             vCounter <= (others => '0');
           ELSE
             vCounter <= vCounter + 1;
           END IF;
         ELSE
           hCounter <= hCounter + 1;
         END IF;
      END IF;
   end process;

   fifo_low <= not fifo_pfull;
fifo : vga_fifo
  PORT MAP (
    wr_clk => fifo_wr_clk,
    rd_clk => clk_vga,
    din => fifo_data,
    wr_en => fifo_wr,
    rd_en => fifoRead,
    dout => fifo_read_data,
    full => open,
    empty => open,
    prog_full => fifo_pfull
  );


   DCM_CLKGEN_inst : DCM_CLKGEN
   generic map (
      CLKFXDV_DIVIDE => 2,       -- CLKFXDV divide value (2, 4, 8, 16, 32)
      CLKFX_DIVIDE   => 14,       -- Divide value - D - (1-256)
      CLKFX_MD_MAX   => 2.0,     -- Specify maximum M/D ratio for timing anlysis
      CLKFX_MULTIPLY => 11,       -- Multiply value - M - (2-256)
      CLKIN_PERIOD   => 20.0,    -- Input clock period specified in nS
      SPREAD_SPECTRUM => "NONE", -- Spread Spectrum mode "NONE", "CENTER_LOW_SPREAD", "CENTER_HIGH_SPREAD",
                                 -- "VIDEO_LINK_M0", "VIDEO_LINK_M1" or "VIDEO_LINK_M2" 
      STARTUP_WAIT => FALSE      -- Delay config DONE until DCM_CLKGEN LOCKED (TRUE/FALSE)
   )
   
   port map (
      CLKIN     => clk,       -- 1-bit input: Input clock
      CLKFX     => clk_vga,   -- 1-bit output: Generated clock output
      CLKFX180  => open,      -- 1-bit output: Generated clock output 180 degree out of phase from CLKFX.
      CLKFXDV   => open,      -- 1-bit output: Divided clock output
      LOCKED    => open,      -- 1-bit output: Locked output
      PROGDONE  => open,      -- 1-bit output: Active high output to indicate the successful re-programming
      STATUS    => open,      -- 2-bit output: DCM_CLKGEN status
      FREEZEDCM => '0',       -- 1-bit input: Prevents frequency adjustments to input clock
      PROGCLK   => clk,       -- 1-bit input: Clock input for M/D reconfiguration
      PROGDATA  => PROG_DATA, -- 1-bit input: Serial data input for M/D reconfiguration
      PROGEN    => PROG_EN,   -- 1-bit input: Active high program enable
      RST       => '0'        -- 1-bit input: Reset input pin
   );
end Behavioral;

testpattern.vhd

----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
-- 
-- Description: Generate a pixel stream for VGA signal
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

Library UNISIM;
use UNISIM.vcomponents.all;

entity testpattern is
    Port ( clk       : in   STD_LOGIC;
           sw        : in   STD_LOGIC_VECTOR(3 downto 0);
           fifo_low  : in   STD_LOGIC;
           fifo_data : out  STD_LOGIC_VECTOR(8 downto 0);
           fifo_wr   : out  STD_LOGIC;
           fifo_wr_clk : out  STD_LOGIC);
end testpattern;

architecture Behavioral of testpattern is
   signal x        : UNSIGNED(10 downto 0) := (others => '0');
   signal y        : UNSIGNED(10 downto 0) := (others => '0');
   signal newFrame : STD_LOGIC := '0';
   
   signal r : STD_LOGIC_VECTOR(2 downto 0) := (others => '0');
   signal g : STD_LOGIC_VECTOR(2 downto 0) := (others => '0');
   signal b : STD_LOGIC_VECTOR(1 downto 0) := (others => '0');

   constant ZERO  : UNSIGNED(10 downto 0) := "00000000000";
   signal xRez    : UNSIGNED(10 downto 0) := ZERO + 640;
   signal yRez    : UNSIGNED(10 downto 0) := ZERO + 480;
   signal clk_sys : std_logic;
   signal clk0    : std_logic;
   signal sw_sync : STD_LOGIC_VECTOR(3 downto 0);
begin

   r <= STD_LOGIC_VECTOR(x(5 downto 3));
   g <= STD_LOGIC_VECTOR(y(5 downto 3));
   b <= std_logic_vector(unsigned(x(5 downto 4)) + unsigned(y(5 downto 4)));
   fifo_data <= newFrame & r & g & b;
   fifo_wr_clk <= clk_sys;
fillFIFO: PROCESS(clk_sys)
   BEGIN
     IF RISING_EDGE(clk_sys) THEN
       newFrame <= '0';
       fifo_WR <= '0';
       -- If the fifo is running low, then push some more data into it.
       IF fifo_low = '1' THEN
         fifo_WR <= '1';
         IF x = xRez - 1 THEN
           -- starting a new line
           x <= (others => '0');
           IF y = yRez - 1 THEN
             -- Starting a new frame
             y <= (others => '0');
             newFrame <= '1';
           ELSE
             y <= y + 1;
           END IF;
         ELSE
           x <= x + 1;
         END IF;
       END IF;

       case sw_sync is
         when "0001" =>
            xRez <= ZERO + 640;
            yRez <= ZERO + 480;
         when "0010" =>
            xRez <= ZERO + 800;
            yRez <= ZERO + 600;            
         when "0100" =>
            xRez <= ZERO + 1024;
            yRez <= ZERO + 768;            
         when "1000" =>
            xRez <= ZERO + 1280;
            yRez <= ZERO + 720;            
         when others =>
        end case;
       sw_sync <= sw;
     END IF;

   END PROCESS;

   ------------------------------------------------------
   -- DCM to generate a 96MHz clock for generating pixels
   ------------------------------------------------------
   DCM_SP_inst : DCM_SP
   generic map (
      CLKDV_DIVIDE => 2.0,                   -- CLKDV divide value
                                             -- (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16).
      CLKFX_DIVIDE => 1,                     -- Divide value on CLKFX outputs - D - (1-32)
      CLKFX_MULTIPLY => 3,                   -- Multiply value on CLKFX outputs - M - (2-32)
      CLKIN_DIVIDE_BY_2 => FALSE,            -- CLKIN divide by two (TRUE/FALSE)
      CLKIN_PERIOD => 10.0,                  -- Input clock period specified in nS
      CLKOUT_PHASE_SHIFT => "NONE",          -- Output phase shift (NONE, FIXED, VARIABLE)
      CLK_FEEDBACK => "1X",                  -- Feedback source (NONE, 1X, 2X)
      DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS
      DFS_FREQUENCY_MODE => "LOW",           -- Unsupported - Do not change value
      DLL_FREQUENCY_MODE => "LOW",           -- Unsupported - Do not change value
      DSS_MODE => "NONE",                    -- Unsupported - Do not change value
      DUTY_CYCLE_CORRECTION => TRUE,         -- Unsupported - Do not change value
      FACTORY_JF => X"c080",                 -- Unsupported - Do not change value
      PHASE_SHIFT => 0,                      -- Amount of fixed phase shift (-255 to 255)
      STARTUP_WAIT => FALSE                  -- Delay config DONE until DCM_SP LOCKED (TRUE/FALSE)
   )
   port map (
      CLK0 => clk0,         -- 1-bit output: 0 degree clock output
      CLK180 => open,     -- 1-bit output: 180 degree clock output
      CLK270 => open,     -- 1-bit output: 270 degree clock output
      CLK2X => open,       -- 1-bit output: 2X clock frequency clock output
      CLK2X180 => open, -- 1-bit output: 2X clock frequency, 180 degree clock output
      CLK90 => open,       -- 1-bit output: 90 degree clock output
      CLKDV => open,       -- 1-bit output: Divided clock output
      CLKFX => clk_sys,       -- 1-bit output: Digital Frequency Synthesizer output (DFS)
      CLKFX180 => open, -- 1-bit output: 180 degree CLKFX output
      LOCKED => open,     -- 1-bit output: DCM_SP Lock Output
      PSDONE => open,     -- 1-bit output: Phase shift done output
      STATUS => open,     -- 8-bit output: DCM_SP status output
      CLKFB => CLK0,       -- 1-bit input: Clock feedback input
      CLKIN => clk,       -- 1-bit input: Clock input
      DSSEN => '0',       -- 1-bit input: Unsupported, specify to GND.
      PSCLK => '0',       -- 1-bit input: Phase shift clock input
      PSEN => '0',         -- 1-bit input: Phase shift enable
      PSINCDEC => '0', -- 1-bit input: Phase shift increment/decrement input
      RST => '0'           -- 1-bit input: Active high reset input
   );
end Behavioral;

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