Async reset

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This FPGA project fails to reset correctly about 5% of the time, when running on my BASYS2 board.

It should just reset "test" to 0s when the button is pushed, then flip the bits on every clock cycle (lighting LEDs 0 and 1).

About one in twenty button pushes it ends up in an inconsistent state, due to different flip-flops exiting reset in different clock cycles.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity async_reset is
    Port ( LEDs   : out STD_LOGIC_VECTOR(7 downto 0);
           switch : in STD_LOGIC;
           clk    : in STD_LOGIC
         );
end async_reset ;

architecture Behavioral of async_reset  is
    signal test : STD_LOGIC_VECTOR(199 downto 0) := (others => '0');
begin
   process (test)
   begin
      if test = x"00000000000000000000000000000000000000000000000000" then
         LEDs <= x"02";
      elsif test = x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" then
         LEDs <= x"01";
      else
         LEDs <= x"FF";
      end if;
   end process;

clk_proc: process(clk,switch)
  begin
     if switch = '1' then
        test <= (others=>'0');
     elsif rising_edge(clk) then
        test <= not test;
     end if;
  end process;
end Behavioral;

# Constraints for Basys2 
NET LEDs(7) LOC = "G1"  |IOSTANDARD=LVTTL;
NET LEDs(6) LOC = "P4"  |IOSTANDARD=LVTTL;
NET LEDs(5) LOC = "N4"  |IOSTANDARD=LVTTL;
NET LEDs(4) LOC = "N5"  |IOSTANDARD=LVTTL;
NET LEDs(3) LOC = "P6"  |IOSTANDARD=LVTTL;
NET LEDs(2) LOC = "P7"  |IOSTANDARD=LVTTL;
NET LEDs(1) LOC = "M11" |IOSTANDARD=LVTTL;
NET LEDs(0) LOC = "M5"  |IOSTANDARD=LVTTL;

NET switch LOC = "G12" | IOSTANDARD=LVTTL;  # Push button 0

NET "Clk" LOC = "B8";
NET "Clk" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 20 ns HIGH 50%;

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