FPGA:Lighting an LED

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This is part of FPGA_course_v2

The aim of this module is pretty simple - just to turn an LED on - but quite a log of ground is covered really quickly.

  • The first thing is we need the circuit design that will light the LED, expressed as VHDL code.
  • The second thing is we need a way to describe how that design is connected to the physical pins on the FPGA chip
  • This then needs to be put together to build a a 'bit' file, that is used to configure the FPGA chip
  • And the finial step is to actually download that '.bit' file to the board.

So lets get down and do it!

Contents

Turning an output pin on in VHDL

Here is the code to turn on a single output - a design called "Light_A_LED" that just sets a single output called "LED" to the value of '1'.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Light_A_LED is
    Port ( LED : out  STD_LOGIC);
end Light_A_LED;

architecture Behavioral of Light_A_LED is
begin
   LED <= '1';
end Behavioral;

The code has three parts. The first two statements declare what libraries we will be using:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

Next is the definition of the external connections external design - the name of the module ('Light_A_LED'), and what signals are connected (just one, 'LED'):

entity Light_A_LED is
    Port ( LED : out  STD_LOGIC);
end Light_A_LED;

And finally the the internal description of the design - how the input and output signals are acted upon. In this case we just set the single output signal to '1':

architecture Behavioral of Light_A_LED is
begin
   LED <= '1';
end Behavioral;

The easiest way make this module from scratch is with the "New Source..." wizard. Create a new empty project that is configured for your FPGA, and then from the 'Project' menu choose 'New Source...'. In the first dialogue box, select "VHDL Module" and enter the name for the module, then click "Next".

This should take you to the "Define Module" page. Just enter a single port called "LED", and change the direction from the default of "in" to "out", then click "Next".

This should take you to the "Summary" page. Check that you have a single port called "LED", with a direction of "out" and click "Finish".

You should end up with a new source module that looks like this:


----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:25:20 03/09/2014 
-- Design Name: 
-- Module Name:    Light_A_LED - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Light_A_LED is
    Port ( j : in  STD_LOGIC);
end Light_A_LED;

architecture Behavioral of Light_A_LED is

begin


end Behavioral;

All the lines that start with "--" are comments, and can all be removed leaving you the shell for your module, where you can add the single missing statement.


Adding the pin constraints

Where you to build this project now and download it to the FPGA, one pin of the FPGA would now be configured as an output and outputting the high logic level. The problem is that it will be any arbitrary pin, and most probably not one connected to your board's light emitting diode.

To resolve this issue a 'constraint' is needed. This serves two purposes, one is to define what pin to use and the other is to define what voltages and currents are being used.

A new source file is required - a Implementation Constraints File (strangely enough called a '.ucf' file). To add one to your project use the "Project / New Source..." menu option again, but this time rather than selecting "VHDL Module" instead select "Implementation Constraints File". I also find that it is easiest to name the file after the development board I am using, making it simpler to use the same project with different boards.

The general format for specifying a signal pin is:

NET [signal name] LOC="[pin name]" | IOSTANDARD=[i/o standard]

The most common I/O standard used is LVTTL, for low voltage (3.3 Volt) TTL signals.

Board specific constraint files

Implementation constraints for Logi-Pi

TBA

Implementation constraints for Logi-Bone

TBA

Implementation constraints for Papilio Pro + Logic Start

NET LED           LOC="P123" | IOSTANDARD=LVTTL;

Implementation constraints for Papilio Duo

TBA

Building the project

In the design panel, clock on the top-level module (in this case called 'Light_A_LED'), and then in the Process window double-click on "Generate Programming file".

With a bit of luck, the 'Synthesize', 'Implement Design' and 'Generate Programming File'steps should complete with errors. There will now be a "Light_A_LED.bit" file in the project's work directory, which can be now be downloaded to your development board.

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