FPGA:Using a switch

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This is part of the FPGA_course_v2

Contents

How to use a switch

If you have successfully completed the previous part of this course, you will now be able to light an LED. The next step is to use a switch to light an LED off and on.

I'm pretty sure that you can guess what your have to do:

1. Add a signal as an input

2. Add a statement to assign the value of the switch input to the LED

3. Add a pin constraint to tell the tools which pin the switch is connected to

However there is a little complication. We need to know how the switch is connected. There is quite a few options - here are the normal ones:

(a) The normal is configuration is that the switch is between a mid-valued resistor and GND, and the other end of resistor is connected to the positive power rail. When the switch is open the FPGA sees the positive power rail, when the switch is closed the FPGA sees 0 V. That is how the LogiPi's DIP switches are wired:

File:LogiPi DIP switches.png

This is common way to wire single-pole switches, especially push buttons, The downside of this design is that when the switch is closed a little power is wasted.

It is 'good form' to include a resistor between the switch and FPGA, to limit current that might be drawn from the FPGA if the input is accidentally configured as an output.

(b) The normal is configuration is that the switch is between a mid-valued resistor and the positive power rail, and the other end of resistor is connected to ground. When the switch is open the FPGA sees 0 V, when the switch is closed the FPGA sees the positive power rail voltage. This is just the inverse of option (a)

(c) The other option is to have a double throw switch, with the FPGA connected to the common contact, and the other contacts connected to either 3.3 V or Ground. That is how the Logicstart's switches are connected:

Logicstart switches.png

Once again, it is 'good form' to include a resistor between the switch's common contact and FPGA, to limit current that might be drawn from the FPGA if the input is accidentally configured as an output.

There are also a few less orthodox designs, which rely on the ability of the FPGA to provide either a weak connection to one of the power rails which eliminates the need for external resistors. This is generally a bad idea, if only because it increases the power that is dissipated within the FPGA.


Updated VHDL source

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Light_A_LED is
    Port ( LED    : out STD_LOGIC;
           switch : in  STD_LOGIC);
end Light_A_LED;

architecture Behavioral of Light_A_LED is
begin
   led <= switch;
end Behavioral;

Board specific constraint files

Constraints for LogiBone

TBA

Constraints for LogiPi

TBA

Constraints for Papilio Duo

TBA

Constraints for Papilio Pro

NET LED           LOC="P123" | IOSTANDARD=LVTTL;
NET SWITCH        LOC="P114" | IOSTANDARD=LVTTL;

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