Genesys2 Mandelbrot

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This FPGA Project was completed in October 2015.

MandelBrot UI.jpg

You can see it in action at and

I now have a Digilent Genesys2 development board, which has an Xilinx Kintex-7 FPGA on it. This is the first time I've used this class of FPGA, so was interested in seeing the difference in performance

Design changes

Only minimal design changes were needed, and the bulk of the work was completed in an evening.

  • A new constraint file was needed (of course)
  • The Genesys2 has a 200MHz Differential clock vs the Nexys Video's 100MHz single ended. This change made it worthwhile to make a separate module for the clocking primitives
  • The Genesys2 has more DSP blocks, allowing for a longer pipeline
  • The Genesys2's LUT logic is faster, allowing 20% of the multipliers to be implemented in LUTs

Apart from these differences the code moved over without any re-coding - for example, the Serialiser based HDMI output just worked.

As a bonus I've added an 8-bit iteration to 24-bit colour lookup table, making it look nicer on the screen.

Performance changes

Without any changes, the design went from just making timing closure to having 0.694 ns of setup slack (for a 4.444 ns clock period). I'm sure that constrained for a higher clock frequency even more performance could be extracted.


All the source is checked into the Github repo at

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