Hidef snow

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This FPGA Project was started and completed in October 2012.

We all know that LCD monitors are perfect. So nothing will annoy the geeky engineer type as much as seeing static on their LCD monitor. Heck! It is all digital, and it doesn't have a tuner built in!

Download this to your FPGA board, connect the Analogue VGA cable to the target's monitor, and then wait for their PC to go to sleep. The monitor will switch over from their digital input to the analogue input, and when they shake the mouse it won't come back.

Oh how I wish I could plug an HDMI version of this into the video distribution system at a TV retailer...

snow.vdl

------------------------------------------------------
-- snow.vhdl - Generates a monochrome static in 1080p
--
-- Engineer - Mike Field <hamster@snap.net.nz>
------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

Library UNISIM;
use UNISIM.vcomponents.all;

entity hidef_snow is
    Port ( clk_32   : in  STD_LOGIC;
           red      : out STD_LOGIC_VECTOR (2 downto 0);
           green    : out STD_LOGIC_VECTOR (2 downto 0);
           blue     : out STD_LOGIC_VECTOR (2 downto 1);
           hsync    : out STD_LOGIC;
           vsync    : out STD_LOGIC);
end hidef_snow;

architecture Behavioral of hidef_snow is
   constant hVisible    : natural := 1920;
   constant hSyncStart  : natural := 1920+32;
   constant hSyncEnd    : natural := 1920+32+696;
   constant hTotalCount : natural := 1920+32+696+32;

   constant vVisible    : natural := 1080;
   constant vSyncStart  : natural := 1080+22;
   constant vSyncEnd    : natural := 1080+22+11;
   constant vTotalCount : natural := 1080+22+11+22;

   signal clk        : std_logic;
   signal nextHsync  : std_logic;
   signal nextVsync  : std_logic;
   signal vCounter   : std_logic_vector(10 downto 0) := (others => '0');
   signal hCounter   : std_logic_vector(11 downto 0) := (others => '0');   
   signal lfsr       : std_logic_vector(31 downto 0) := (others => '1');
   signal feedback   : std_logic;
begin

   feedback <= lfsr(31) xor lfsr(21) xor lfsr(1) xor lfsr(0);
	
clocking : DCM_SP
   generic map( CLK_FEEDBACK      => "1X",
            CLKDV_DIVIDE          => 2.0,
            CLKFX_DIVIDE          => 3,
            CLKFX_MULTIPLY        => 14,
            CLKIN_DIVIDE_BY_2     => FALSE,
            CLKIN_PERIOD          => 31.250,
            CLKOUT_PHASE_SHIFT    => "NONE",
            DESKEW_ADJUST         => "SYSTEM_SYNCHRONOUS",
            DFS_FREQUENCY_MODE    => "LOW",
            DLL_FREQUENCY_MODE    => "LOW",
            DUTY_CYCLE_CORRECTION => TRUE,
            FACTORY_JF            => x"C080",
            PHASE_SHIFT           => 0,
            STARTUP_WAIT          => FALSE)
      port map (CLKFB   => open,
                CLKIN   => clk_32,
                DSSEN   => '0',
                PSCLK   => '0',
                PSEN    => '0',
                PSINCDEC=> '0',
                RST     => '0',
                CLKDV   => open,
                CLKFX   => clk,
                CLKFX180=> open,
                CLK0    => open,
                CLK2X   => open,
                CLK2X180=> open,
                CLK90   => open,
                CLK180  => open,
                CLK270  => open,
                LOCKED  => open,
                PSDONE  => open,
                STATUS  => open);
      
   process(clk)
   begin
      if rising_edge(clk) then
         hsync <= nextHsync;
         vsync <= nextVsync;
         lfsr <= lfsr(30 downto 0) & feedback;

         if hCounter < hVisible and vCounter < vVisible then
            red   <= lfsr(0) & lfsr(0) & lfsr(0);
            green <= lfsr(0) & lfsr(0) & lfsr(0);
            blue  <= lfsr(0) & lfsr(0);
         else
            red   <= (others=>'0');
            green <= (others=>'0');
            blue  <= (others=>'0');
         end if;
         
         if hCounter /= hTotalCount-1 then
            hcounter <= hcounter+1;
         else
            hcounter <= (others => '0');       
            if vCounter = vTotalCount-1 then
               vCounter <= (others => '0');
            else
               vCounter <= vCounter+1;
            end if;
         end if;

         if hcounter >= hSyncStart and hcounter < hSyncEnd then
            nextHsync <= '0';
         else
            nextHsync <= '1';
         end if;
      
         if vcounter >= vSyncStart and vcounter < vSyncEnd then
            nextVsync <= '1';
         else
            nextVsync <= '0';
         end if;
      end if;
   end process;
end Behavioral;

snow.ucf

Constraints for the Papilio One + LogicStart MegaWing

NET "clk_32" LOC = "P89" | IOSTANDARD = LVTTL | PERIOD = 31.25ns ;

NET Blue(1)     LOC="P78"  | IOSTANDARD=LVTTL;  # B1
NET Blue(2)     LOC="P71"  | IOSTANDARD=LVTTL;  # B2

NET Green(0)    LOC="P68"  | IOSTANDARD=LVTTL;  # B4
NET Green(1)    LOC="P66"  | IOSTANDARD=LVTTL;  # B5
NET Green(2)    LOC="P63"  | IOSTANDARD=LVTTL;  # B6

NET Red(0)      LOC="P61" | IOSTANDARD=LVTTL;  # C4
NET Red(1)      LOC="P58" | IOSTANDARD=LVTTL;  # C5
NET Red(2)      LOC="P54" | IOSTANDARD=LVTTL;  # C6

NET vSync       LOC="P85" | IOSTANDARD=LVTTL;  # C2
NET hSync       LOC="P83" | IOSTANDARD=LVTTL;  # C3

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