If vs case

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This FPGA Project is a little experiment in the difference between using CASE and IF in VHDL.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ifvscase is
    Port ( clk : in  STD_LOGIC;
           a : in  STD_LOGIC;
           b : in  STD_LOGIC;
           c : in  STD_LOGIC;
           count : out  STD_LOGIC_VECTOR(7 downto 0));
end ifvscase;

architecture Behavioral of ifvscase is
   signal counter   : unsigned(7 downto 0) := (others => '0');
   signal case_var  : std_logic_vector(2 downto 0);
begin
   count <= std_logic_vector(counter(7 downto 0));
   case_var <= a&b&c;
   
   process(clk)
      variable increment : unsigned(7 downto 0) := (others => '0');
   begin
      if rising_edge(clk) then
      
      -- using ifs  : Minimum period:   3.940ns{1}   (Maximum frequency: 253.807MHz) 
      --   if a = '0' then
      --      if b = '0' then
      --         if c = '0' then
      --            counter <= counter+3;  -- 000
      --         else
      --            counter <= counter+2;  -- 001
      --         end if;
      --      else
      --         if c = '0' then
      --            counter <= counter+7;  -- 010
      --         else
      --            counter <= counter;    -- 011
      --         end if;
      --      end if;
      --   else
      --      if c = '0' then
      --         counter <= counter;     -- 1X0
      --      else
      --         counter <= counter+11;  -- 1X1
      --      end if;
      --   end if;
         
      --    using case Design Minimum period:   4.474ns{1}   (Maximum frequency: 223.514MHz) 
      --   case case_var is
      --      when "000" => counter <= counter+3;
      --      when "001" => counter <= counter+2;
      --      when "010" => counter <= counter+7;
      --      when "011" => counter <= counter;
      --      when "100" => counter <= counter;
      --      when "101" => counter <= counter+11;
      --      when "110" => counter <= counter;
      --      when others => counter <= counter+11;
      --   end case;
      
      --    using case Design #2   Minimum period:   4.543ns{1}   (Maximum frequency: 220.119MHz)  
      --   case case_var is
      --      when "000" => counter <= counter+3;
      --      when "001" => counter <= counter+2;
      --      when "010" => counter <= counter+7;
      --      when "101" => counter <= counter+11;
      --      when "111" => counter <= counter+11;
      --      when others => counter <= counter;
      --   end case;
      
      -- Design #4a - using CASE to select the increment, and a single adder (Minimum period:   3.491ns{1}   (Maximum frequency: 286.451MHz) 
         case case_var is
            when "000" => increment := x"03";
            when "001" => increment := x"02";
            when "010" => increment := x"07";
            when "101" => increment := x"0B";
            when "111" => increment := x"0B";
            when others => increment := x"00";
         end case;
         counter <= counter + increment;
      
      -- Design #4b - using IF to select the increment, and a single adder  Minimum period:   3.491ns{1}   (Maximum frequency: 286.451MHz)  
      --   if a = '0' then
      --      if b = '0' then
      --         if c = '0' then
      --            increment := x"03";  -- 000
      --         else
      --            increment := x"02";  -- 001
      --         end if;
      --      else
      --         if c = '0' then
      --            increment := x"07";  -- 010
      --         else
      --            increment := x"00";  -- 011
      --         end if;
      --      end if;
      --   else
      --      if c = '0' then
      --         increment := x"00";     -- 1X0
      --      else
      --         increment := x"0B";     -- 1X1
      --      end if;
      --   end if;
      --   counter <= counter + increment;
      
      end if;
   end process;
end Behavioral;

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