Log Pins

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This FPGA_Projects was completed in Feb 2015, and thanks to dstorm19 for the idea.

Here is a small bit of code that will log the state of the test_probes signal to a host as ASCII over RS232. It doesn't locally buffer the data, and as the message is 130 bits long the maximum update rates is 9600/130 = 73Hz or so. If you run it at a higher baud rate then you will get updates more often.

You will need to replace 32000000 and 9600 with your FPGA's clock speed and baud rate, as well as providing a suitable constraints file.

---------------------------------------------
-- Log_pins.vhd - Logging the start of 11 pins
--                to a PC over RS232
--
-- Author: Mike Field <hamster@snap.net.nz>
-----------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity log_pins is
    Port ( clk32       : in  STD_LOGIC;
           test_probes : in  STD_LOGIC_VECTOR (10 downto 0);
           rs232_tx    : out  STD_LOGIC);
end log_pins;

architecture Behavioral of log_pins is
   signal current_inputs        : std_logic_vector(10 downto 0)     := (others => '0');
   signal last_sent             : std_logic_vector(10 downto 0)     := (others => '0');
   signal clocks_ticks_per_baud : unsigned(11 downto 0)             := to_unsigned(32000000/9600,12);
   signal count                 : unsigned(11 downto 0)             := (others => '0');
   signal message               : std_logic_vector(10*13-1 downto 0):= (others => '1');
   signal bits_to_send          : unsigned(7 downto 0)              := (others => '1');
   signal startup               : std_logic                         := '1';
begin
  -- The TX output is the LSB of the message buffer
  rs232_tx <= message(0);

clk_proc: process(clk32)
   begin
      if rising_edge(clk32) then
           -- are we sending bits?
           if bits_to_send /= 0 then
                if count = clocks_ticks_per_baud-1 then
                    -- Move on to the next bit
                    message      <= '1' & message(message'high downto 1);
                    bits_to_send <= bits_to_send - 1;
                    count        <= (others => '0');
                else
                    count <= count+1;
                end if;
           else
               -- Are the inputs still the same as last time?
               if current_inputs /= last_sent or startup = '1' then
                 for i in 0 to 10 loop
                     if current_inputs(i) = '1' then
                        message(i*10+9 downto i*10) <= "1001100010"; -- ASCII '1'
                     else
                        message(i*10+9 downto i*10) <= "1001100000"; -- ASCII '0'
                     end if;
                  end loop;   
                  message(119 downto 110) <= "1000010100"; -- ASCII 10, new Line.
                  message(129 downto 120) <= "1000011010"; -- ASCII 13, new Line.
                  bits_to_send <= to_unsigned(message'high,8);
                  last_sent    <= current_inputs;
                  count        <= (others => '0');
                  startup      <= '0';
               end if;
           end if;
           -- A single stage of clock synchronization - most likely not enough!
           current_inputs <= test_probes;
        end if;
     end process;
end Behavioral;

And here is the contraints file for the Papilio One:

NET CLK32             LOC="P89"  | IOSTANDARD=LVTTL | PERIOD=31.25ns;               # CLK
NET rs232_TX          LOC="P90"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # RX

NET test_probes(0)    LOC="P91"  | IOSTANDARD=LVTTL;                                # C0 Switch
NET test_probes(1)    LOC="P92"  | IOSTANDARD=LVTTL;                                # C1 Switch
NET test_probes(2)    LOC="P94"  | IOSTANDARD=LVTTL;                                # C2 Switch
NET test_probes(3)    LOC="P95"  | IOSTANDARD=LVTTL;                                # C3 Switch
NET test_probes(4)    LOC="P98"  | IOSTANDARD=LVTTL;                                # C4 Switch
NET test_probes(5)    LOC="P2"   | IOSTANDARD=LVTTL;                                # C5 Switch
NET test_probes(6)    LOC="P3"   | IOSTANDARD=LVTTL;                                # C6 Switch
NET test_probes(7)    LOC="P4"   | IOSTANDARD=LVTTL;                                # C7 Switch
NET test_probes(8)    LOC="P36"  | IOSTANDARD=LVTTL;                                # B11 Joystick 
NET test_probes(9)    LOC="P34"  | IOSTANDARD=LVTTL;                                # B12 Joystick 
NET test_probes(10)   LOC="P22"  | IOSTANDARD=LVTTL;                                # B15 Joystick 

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