Logic Analyser Test

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This FPGA Project was completed in March 2014.

I've got myself a Rigol 1102D, that includes a 16 channel Logic Analyser. I wanted to see what speeds it is useful at, so made this wee project.

LAT test setup.jpg

Contents

What I'm doing

I'm using a Papilio Pro FPGA board, and multiplying the 32MHz clock by 25/8 to give 100MHz, and then using that to drive a counter.

The lowest 7 bits of counter provide bits 7 to 1 of the 8-bit output. The lest significant output bit is being driven by a DDR register that is set up to forward out the 100MHz clock. This makes it look like the output of an 8-bit counter running at 200MHz:

Lat sim.jpg

This gives transitions every 5ns, 10ns, 20ns, 40ns, 80ns, 160ns, 320ns and 640ns to capture with the Logic Analyser.

I've also made the counter long enough to blink an LED, just to confirm that the project is running.

Results

To use the project it is synthesized, downloaded to the FPGA, and the logic analyser hooked up to the C0 - C7 pins and GND. The trigger is set for an edge of the C7 output. This is what it captures:

Lat noisy.jpg

Hum - not what I was expecting.

Removing the fastest two signals (with 5ns & 10ns transitions) got rid of all of the noise.

Lat clean persist.jpg

With display persistence turned off, and in single capture mode you get a decent display of what is going on.

Lat clean.jpg

Time resolution seems to be about 5ns

Lat resolution.jpg

Turning down the FPGA's drive strength to 2mA on all outputs allowed the 10ns signal to be captured without corrupting the others, however it is pretty patchy:

Lat 100Mhz.jpg

I tested again with 15.2 ns signal, and I was hoping that both the 15.2 ns and 30 ns signals display accurately enough to be useful. And they did:

Lat 66MHz.jpg

My Conclusions

The Rigol 1102D looks to be perfect for looking a logic signals clocked at up to 66Mhz (15.2ns) but is out of its depth at 100MHz - I guess this is pretty much due to its 5ns sampling resolution.

As clock signals have twice as many transitions as the other signals I suspect that if you also want to display the clock signal you will be limited speeds of around 33MHz or so. Also, you have to be careful with drive strengths to maintain signal integrity...

Source files

LogicAnalyserTest.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;

entity LogicAnalyserTest is
    Port ( clk32 : in  STD_LOGIC;
           led    : out STD_LOGIC;
           test_signals : out  STD_LOGIC_VECTOR (7 downto 0));
end LogicAnalyserTest;

architecture Behavioral of LogicAnalyserTest is
   signal counter : unsigned(26 downto 0) := (others => '0');
   signal clkfb   : std_logic;
   signal clk100  : std_logic;
begin

PLL_BASE_inst : PLL_BASE
   generic map (
      BANDWIDTH => "OPTIMIZED",
      CLKFBOUT_MULT => 25,
      CLKFBOUT_PHASE => 0.0,
      CLKIN_PERIOD => 31.25,      
      CLKOUT0_DIVIDE => 8,
      CLKOUT1_DIVIDE => 8,
      CLKOUT2_DIVIDE => 8,
      CLKOUT3_DIVIDE => 8,
      CLKOUT4_DIVIDE => 8,
      CLKOUT5_DIVIDE => 8,
      CLKOUT0_DUTY_CYCLE => 0.5,
      CLKOUT1_DUTY_CYCLE => 0.5,
      CLKOUT2_DUTY_CYCLE => 0.5,
      CLKOUT3_DUTY_CYCLE => 0.5,
      CLKOUT4_DUTY_CYCLE => 0.5,
      CLKOUT5_DUTY_CYCLE => 0.5,
      CLKOUT0_PHASE => 0.0,
      CLKOUT1_PHASE => 0.0,
      CLKOUT2_PHASE => 0.0,
      CLKOUT3_PHASE => 0.0,
      CLKOUT4_PHASE => 0.0,
      CLKOUT5_PHASE => 0.0,
      CLK_FEEDBACK => "CLKFBOUT",
      COMPENSATION => "SYSTEM_SYNCHRONOUS",
      DIVCLK_DIVIDE => 1,
      REF_JITTER => 0.1,
      RESET_ON_LOSS_OF_LOCK => FALSE
   )
   
   port map (
      CLKFBOUT => CLKFB,
      CLKOUT0  => clk100,
      CLKOUT1  => open,
      CLKOUT2  => open,
      CLKOUT3  => open,
      CLKOUT4  => open,
      CLKOUT5  => open,
      LOCKED   => open, 
      CLKFBIN  => CLKFB,
      CLKIN    => CLK32,
      RST      => '0'
   );
  ODDR2_inst : ODDR2
   generic map(DDR_ALIGNMENT => "NONE",INIT => '0',SRTYPE => "SYNC")
   port map (
      Q => test_signals(0), 
      C0 => clk100,
      C1 => not clk100,
      CE => '1', 
      D0 => '0',
      D1 => '1',
      R => '0',
      S => '0'
   );
   
process(clk100)
   begin
      if rising_edge(clk100) then
         test_signals(7 downto 1) <= std_logic_vector(counter(6 downto 0));
         led <= counter(counter'high);
         counter <= counter+1;
      end if;
   end process;
end Behavioral;

LogicAnalyserTest.ucf

# Constraints file for the Papilio Pro 
#
NET CLK32   LOC="P94"  | IOSTANDARD=LVTTL | PERIOD=31.25ns;
#
# [GND] [C00] P114
# [2V5] [C01] P115
# [3V3] [C02] P116
# [5V0] [C03] P117
#       [C04] P118
#       [C05] P119
#       [C06] P120
#       [C07] P121
#
NET test_signals(0) LOC="P114" | IOSTANDARD=LVTTL | DRIVE=2;
NET test_signals(1) LOC="P115" | IOSTANDARD=LVTTL | DRIVE=2;
NET test_signals(2) LOC="P116" | IOSTANDARD=LVTTL | DRIVE=2;
NET test_signals(3) LOC="P117" | IOSTANDARD=LVTTL | DRIVE=2;
NET test_signals(4) LOC="P118" | IOSTANDARD=LVTTL | DRIVE=2;
NET test_signals(5) LOC="P119" | IOSTANDARD=LVTTL | DRIVE=2;
NET test_signals(6) LOC="P120" | IOSTANDARD=LVTTL | DRIVE=2;
NET test_signals(7) LOC="P121" | IOSTANDARD=LVTTL | DRIVE=2;
#
NET LED LOC="P112" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW;

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