Mandelbrot NG 1080i
From Hamsterworks Wiki!
This FPGA Project was completed in July 2015.
A very shaky video of this in action is at https://youtu.be/4fCQMh3WhB0
As far as I know this fractal view is unique.
- Has no frame buffer - each pixel is recalculated every time.
- Displays at 1920x1080 resolution
- Smooth real-time pans and zooms
- about 120 billion calculations per second.
All clocks all generated in the same MMCM - it is a requirement for the serializers that the clocks come from the came MMCM.
The clocking is derived as follows:
- The 100MHz system is divided by 4, to give 25 MHz
- That is multiplied by 44.5, to give 1,112.5 MHz for the VCO frequency, just inside the high end of the FPGA's range.
- The VCO is then divided by 15 for the Pixel clock (74.166 MHz - about 0.11% off of the VESA standard 74.25 MHz )
- The VCO clock is divided by 3 to give x5 the pixel clock for the output serializers (370.83 MHz)
- The VCO is also divided by 5 to give the clock for the calculations (222.5 MHz)
Because these are all phase aligned their is minimal clock domain crossing issues.
How to generate 1080i video
It is hard to find exact details on how 1080i works. However it is pretty simple.
1. The even lines of the image are displayed, (0,2,4,6.... 1078)
2. There are then 23 lines of vertical blanking
3. The odd lines of the image are displayed (1,3,5,7.... 1079)
4. There are then 22 lines of blanking.
During the first blanking signal, the VSYNC is asserted for two lines times, starting half way through the third line of the blanking period (when referenced to the HSYNC signal).
For the second blanking period VSYNC is asserted for two lines, starting at the start of the third line (when referenced to the HSYNC signal).
The display sees the difference in VSYNC's phase alignment, and recognizes it as an interlaced signal. If you think about how a full analog CRT work, it makes perfect sense.
Elaborated RTL design
The elaborated design shows how it forms a very long chain of calculation stages, where apart from sharing the clock signal every thing just feeds to/from the prior stage:
Timing closure is comfortably made, but not enough that performance can be increased:
Prebuilt bit file
This includes everything needed creating a project for the Nexys Video, except the 17x17 unsigned multiplier IP block. Make sure you set the multiplier latency to 4 cycles!