MiniSpartan6+ DVID Logo

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This FPGA Project was completed in Jan 2015.

This project overlays the Hamsterworks logo on the top corner of a 720p/60Hz DVI-D video stream. It can be used as a base for image processing projects. It uses the Scarab Hardware Scarab miniSpartan6+ FPGA development board.

Dvid logo.jpg

So what is going on?

The processing of the DVI-D signal is as follows:

  1. DVI-D input
    1. The DVI-D input signals are sent through differential input buffers, set to receive TMDS signals, in this case from a Western Digital HD Live media player.
    2. The DVI-D clock signal is fed into a PLL to generate the x1, x2 and x10 signals. Due to the settings of the PLL this will only work for pixel clocks between 40 MHz and 100 MHz. You can alter the constants to make it work from 20 MHz to 50 MHz if desired
    3. These clocks are used to drive three ISERDES2 serialisers to capture 5 bits every tick of the x2 clock
    4. These are stitched back together to produce a 10-bit symbol for each channel for each pixel
    5. These symbols are monitored for a sync codeword, and if it isn't seen then the alignment of the 10-bit symbols is slipped one bit
    6. The 10-bit symbols are passed through a TMDS 10b/8b decoder to recover the original pixel colours, and the blank, hsync and vsync signals - the standard VGA signals. These are output along with the pixel clock.
  2. The recovered VGA signals are then passed through a module that inserts a 128x128 logo in the top right corner
  3. DVID Output
    1. This is then passed into the DVI-D output module
    2. The pixel colour values are passed through TMDS 8b/10b encoders - the sync signals are combined in the channel 0
    3. A second PLL is used to generate a x2 and x10 signal
    4. The TMDS symbols are split in half and feed into three 5-bit OSERDES2 serializers, and one more serializer is used to generate the TMDS clock signal. These serializers are driven by the x2 and x10 clock
    5. The resulting bit streams are sent out through the differential output drivers.

Currently the project does not include an EDID serial ROM, so you may need to work some magic on the source device to set the output resolution and colour depth.

Source Project

The source project contains no generated IP blocks, so nothing is hidden away. This is an improvement over the earlier DVI-D output project that required generation of a small IP FIFO.


The logo was generated from the Hamsterworks graphic as follows:

  1. Open the image in MS-Paint.
  2. Resize the graphic to 128x128
  3. Save it as a 24-bit BMP file
  4. Use the following 'C' program to dump out the pixel colours in a format that can be used to replace the data currently in "logo.vhd":
* logo.c : A hack to dump pixels from a 24-bit
*          BMP file, in a format suited to be
*          included in a VHDL file
* Author : Mike Field <>
#include <stdio.h>

int main(int argc, char *argv[])
  int i;
  FILE *f;
  if(argc != 2) {
    fprintf(stderr,"Please give file name\r\n");
    return -1;

  f = fopen(argv[1],"rb");
  if(f == NULL) {
    fprintf(stderr,"Unable to open file\r\n");
    return -1;

  /* Skipping the BMP header */
  for(i = 0; i < 54; i++)

  /* Dumping out the pixels */
  i = 0;
  while(1) {
    int c0,c1,c2;
    c0 = getc(f);
    c1 = getc(f);
    c2 = getc(f);
    /* End of file? */
    if(c0 < 0 || c1 < 0 || c2 < 0)

    /* Comma needed after last number? */
    if(i > 0) {
      /* NL+CR needed after last number? */
      if((i&7) == 0)

    /* Output this number */
  return 0;

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