MiniSpartan6+ DVID Output

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This FPGA Project was completed in Jan 2015.

To make the most of the Scarab miniSpartan6+ I've slightly reworked my DVI-D output design, making it a bit more self contained. The component now encapsulates all the clocking, and provides a nice clean interface:

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-- Convert the VGA signals to the DVI-D/TMDS output 
---------------------------------------------------
Inst_dvid_out: dvid_out PORT MAP(
      -- Clocking
      clk_pixel  => pixel_clock,
      -- VGA signals
      red_p      => red_p,
      green_p    => green_p,
      blue_p     => blue_p,
      blank      => blank,
      hsync      => hsync,
      vsync      => vsync,
      -- TMDS outputs
      tmds_out_p => hdmi_out_p,
      tmds_out_n => hdmi_out_n
   );

Due to the PLL frequency limits of the Spartan 6, changes need to be made to the PLL settings to select two pixel clock ranges, 25Mhz to 50MHz or 40MHz to 100MHz. See dvid_out_clocking.vhd for details.

Source project

Rather then posting source code, here is the entire project in a zip file:

File:MiniSpartan6 plus dvid output.zip

Building the missing FIFO

Due to licensing I have not included the output FIFO in the project archive. You will need to create it using the "Project/New Source..." option.

  • Select "IP"
  • Call it 'tmds_out_fifo'
  • From "Memories and Storage Elements/FIFOs" select "FIFO Generator"
  • Select 'Next' then 'Finish' to bring up the FIFO Generator wizard
  • Select 'Native', then click 'Next'
  • Select 'Independent Clocks (Distributed RAM)', then click 'Next'
  • Select 'Standard FIFO', write width of 30 and write depth of 16, then click 'Next'
  • Leave all optional flags unchecked, then click 'Next'
  • Unselect the "Reset pin", and select "Multiple Programmable Empty Thresholds". Set the limits to 2 and 8 for the assert and negate values, then click 'Next'
  • Leave all Data Count Options unchecked, then click 'Next'
  • Click 'Generate', then wait
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