Module 15

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Please make sure that you have completed the earlier modules of FPGA course.

Having problems with your code? Do I need to change something? Want a reference solution to the project? Email me at "", after removing the "nospam-" bit. I'll try to get back to you in a day or so.


Aims of module

  • A quick introduction of the Digital Clock Manager resource
  • Build a project that uses them.

Note for BASYS2 users

Because of jitter the DCM may have touble locking onto the incoming clock. This hasn't been a problem for me, but it may be an issue for you.

What are Digital Clock Managers?

The Spartan 3 FPGA family have dedicated blocks called Digital Clock Managers (DCMs). These receive an incoming clock and can do the following an more:

  • Generate a faster or slower clock signal using an input clock as a reference
  • Generate signals with a known phase shift (e.g. 90, 180 or 270 degrees out of phase
  • Correct clock duty cycles, ensuring that the high and low times are 50%.
  • Phase shift the internal FPGA clock signals to compensate for internal clock distribution delays

DCMs can also be cascaded, allowing multiple clocks to be used (e.g. one for controlling memory, and one for the VGA pixel clock

Because of this flexibility they are quite complex to use. I find using the Core Generator is the best way configure a DCM.

Using the Wizard

Pick any project you like, and add a "New Source", using the "IP (Core Generator...) option to create a component "my_dcm":


One again choose the "Only IP compatible with chosen part" option, then drill down to "Single DCM_SP":


Click "Next" then "Finish" to start the Core Generator.

You will then be presented with this dialog box:


Just click "OK" to open the Clocking Wizard's General Setup dialogue box:

Here you can choose what signals you will use and set the input clock frequency. The most common outputs I use is the CLKFX (which is the synthesized output frequency). You may want to untick the RST (reset) signal if this is the only clock for the entire project:


The next screen allows you to choose what clock buffers are being used. For most projects you will use "Global Buffers" - being global the clock signal is available to all logic on the FPGA:


The next screen is the interesting one - it's where you get to set the output frequency. Input the desired frequency and press "Calculate":


You will now get the summary screen, where you can click "Finish":


Once generated you will be able to use the instantiation templates to add a "my_dcm" component to your project.

Project 15.1 - Use a DCM

  • Add a DCM to one of your projects (e.g. project 4.1). Remember to update no only the signal monitored by rising_edge(), but also the signal used on the process sensitivity list. If using a Basys2 board it may pay to connect a LED to the LOCKED signal, allowing you to verify if the DCM can synchronize with the source clock.

Ready to carry on?

Click here to carry on to the next module.

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