Module 3

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Please make sure that you have completed the earlier modules in the FPGA course

Having problems with your code? Do I need to change something? Want a reference solution to the project? Email me at "nospam-hamster@snap.net.nz", after removing the "nospam-" bit. I'll try to get back to you in a day or so.

Contents

Aim of project

Experiment with binary operations in VHDL.

This project is much easier than Module 2, as you will only be changing one or two lines in your existing design, but there are a few short challenges with a lot more thinking and problem solving.

Learning outcomes

  • Refresh on binary operators
  • Using constants STD_LOGIC values
  • Combine one or more signals to generate an output
  • Test the design in hardware
  • Building familiarity with the design tools
  • Insights into digital logic

STD_LOGIC

As previously mentioned, a STD_LOGIC signal is analogous to a wire carrying a single bit of data.

Confusingly it is a lot more. Each can take on one of 9 different values at any one time!

For most designs only three are used

Value Meaning
'0' Logical 'Low'
'1' Logical 'High'
'Z' High impedance (only used on bidirectional signals)

It is important to note that these values are not numbers - they in the source code they are enclosed in a single quote (').

The 'Z' state does not actually happen in the FPGA these days. Apart from on the input/output pins no tristate logic exists within an FPGA - it is all mapped to multiplexer. Because of this using tristate logic for internal buses isn't recommended - the synthesis software has to do more work.

Of the other five values there are "Weak high" ('H'), "Weak low" ('L') that are mostly in interfacing and the "Uninitialised" ('U'), "Weak Uninitialised" ('W'), "Forcing unknown" ('X'), and "don't care" ('-') that are only seen when simulating a design.

Boolean operations

Usually you will only come across four Boolean operations

Operation Result
NOT x Result is '0' when x is '1', otherwise '1'
x AND y Result is '1' when both x and y are '1', otherwise '0'
x OR y Result is '1' when either x is '1' or y is '1', otherwise '0'
x XOR y Result is '1' when only one of either x or y are '1', otherwise '0'

Two other elementary binary operations are supported:

Operation Equivalent expression
x NAND y NOT(x AND y)
x NOR y NOT(x OR y)

Using these operators in VHDL

Using these operators is pretty simple. If you open up the project from Module 2 and make the changes to lines 13 and 14 as follows:

 1: library IEEE;
 2: use IEEE.STD_LOGIC_1164.ALL;
 3:
 4: entity Switches_LEDs is
 5:   Port ( switch_0 : in  STD_LOGIC;
 6:          switch_1 : in  STD_LOGIC;
 7:          LED_0 : out  STD_LOGIC;
 8:          LED_1 : out  STD_LOGIC);
 9: end Switches_LEDs;
10:
11: architecture Behavioral of Switches_LEDs is
12: begin
13:   LED_0 <= switch_0 AND switch_1;
14:   LED_1 <= switch_0 OR switch_1;
15: end Behavioral;

Using the instructions in Module 2 you will now be able to build this project and download it to your FPGA.

Project 3.1

  • Compare switch_0 NAND switch_1 with NOT(switch_0 AND switch_1)
  • Compare switch_0 NAND switch_1 with NOT(switch_0) OR NOT(switch_1)
  • Compare NOT(switch_0) with switch_0 XOR switch_1, when switch 1 is on.

Challenges

  • Can you make a design that will only light a LED when switch_0 is off and switch_1 is on?
  • Can you make a AND operator out of only OR and NOT operations?
  • Can you make a OR operator out of only AND and NOT operations?
  • Can you make a OR operator out of only NOR operations? (hint, you can use the input values more than once)
  • Experiment with XOR. Can you make an equivalent function out of only AND, OR and NOT?

Further thinking

  • Are any of these operations are "fundamental", as all other operations can be built from them?
  • For the operations that are not "fundamental", what are they missing?

Ready to carry on?

Click here to carry on to the next module.

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