MyStorm Blackice

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This FPGA project was completed in January 2017.

Clifford Wolf's IceStorm project ( is a fully Open Source FPGA EDA flow. It runs from Verilog through to the programming bitmap file, but at the moment only supports Lattice iCE40 FPGAs.

This is my first attempt at using the MyStorm Blackice by Alan Wood and Ken Boak - you can find more about it at



Setting up the tools

Here are the steps I used to get my first project running.

1. Installed a plain-vanilla install of Ubuntu 16.04.1 LTS in a VM. With all the tools installed and built you will need 11 GB of disk space, so I'm using a 16GB disk. I created a single user account - 'hamster'

2. Added the required dependencies (see for the latest list):

 sudo apt-get install build-essential clang bison flex libreadline-dev \
                      gawk tcl-dev libffi-dev git mercurial graphviz   \
                      xdot pkg-config python python3 libftdi-dev 
 I also added "screen" which is used to monitor the programming process

3. Cloned the required Github repos:

 git clone icestorm
 git clone yosys
 git clone arachne-pnr

4. Build the tools (this can take a while!):

 for i in icestorm yosys arachne-pnr
   cd $i

5. Install the tools:

 for i in icestorm yosys arachne-pnr
   cd $i
   sudo make install

First design

As always, the first design is to blink an LED or two. Not being familiar with the board I wanted to blink LEDs on one of the PMOD connectors.

My learning along the way...

  • The Blackice board has a 4k part, but it will, um, accept bit files for the 8k and still work, but you need to specify the device an package correctly during the place and route process (see the device and package settings in the Makefile below). Look at the table of supported devices in to see what options should be used for arachne-pnr and icetime programs.
  • The programming for the Blackice board is somewhat unique - you just throw the bitmap file at the serial port.

blink.v - the HDL code

module blink (
    input sysclk_100,
    output [3:0] led

   reg always_off = 1'b0;
   reg [32:0] counter;

   always @ (posedge sysclk_100) begin
       led <= counter[26:23];
       counter <= counter + 1;

blink.pcf - the physical constraints for the place and route process

This is the clock constraint, and the four pins on the PMOD5 connector.

set_io sysclk_100  129
set_io led[0]      143
set_io led[1]      114
set_io led[2]      112
set_io led[3]      107

Makefile - the script to build the project

To build the bitfile just type "make". To program type "make prog".

I have put all the flow in one make target, which is most probably poor form!

blink.bin: blink.v blink.pcf
        yosys -p "synth_ice40 -blif blink.blif" blink.v
        arachne-pnr --device 8k --package tq144:4k -p blink.pcf blink.blif -o blink.asc
        icepack blink.asc blink.bin
        icetime -d hx8k -P tq144:4k -mt blink.asc

prog: blink.bin
        sudo bash -c "cat blink.bin > /dev/ttyUSB0"


Once blink.bin was successfully built, I then:

1. Attach the LEDs to PMOD5. I was using a board I built ages ago to work with a Papilio board

2. attach the FPGA board to my Laptop, map the USB device through to the virtual machine

3. Check 'dmesg' to see that the device has shown up as /dev/ttyUSB0

4. Open a second terminal and run "screen" to monitor any chatter from the board:

 sudo screen /dev/ttyUSB0 115200

5. Run "make prog" to stream the bitmap file to the FPGA

6. Look on in amazement as the LEDs blink!

Final notes

1. The design flow is fast, especially for small designs I've tested, making it very well suited for classroom use. It also needs minimal PC resources

2. Treating the -4k device as a -8k chip is only vaguely documented, and was a stumbling block

3. It is very much OpenSource - no licensing, all the source there. The only $ cost is the Development board.

4. You can get a full environment up and running in a VM way quicker than using Xilinx or Altera tools, with their multi-GB downloads.

5. It is Verilog only at the moment. Time for me to learn another HDL I guess!

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