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Papilio Plus has a single clock running at 32MHz.
NET CLK LOC = "P94" | IOSTANDARD = LVTTL33 | PERIOD = 31.25ns;
Generating other useful frequencies
By using the DCM on the FPGA other frequencies can be synthesized. The incoming clock can be multiplied by an integer from 2 through 32, then divided by an integer from 1 through 32 - nearly 500 options. I'm not sure, but due to the frequency limits of a DCM using any multiplier greater than 10 might exceed its Fmax.
Here is a handy table of multiplied clock rates, allowing an quick way of finding something that will divide close to your target frequency
For example, if you were wanting to generate something close to 25MHz, 224MHz is pretty close to 225MHz, so using Cin*7/9 = 24.888MHz might be good enough, or maybe Cin*4/5 = 25.6MHz.
Mark Schafer sent me a pair of Python scripts that can help find your ideal clock ratios - File:Papilio clock.zip