Papilio Plus/Colour Test

From Hamsterworks Wiki!

Jump to: navigation, search

This Papilio Plus project tests the basic Papilio Plus/VGA colours by displaying the full colour pallet on the screen.The screen runs in 800x600 @ 60Hz, requiring an 40MHz pixel clock.

As well as the code below, an IP core is required for "Clk40". Use the "Clocking Wizard" IP Core to take the 32MHz clock and generate a single Clk40 output running at 40MHz (multiply by five, divide by four).

ColourTest.ucf

NET CLK  LOC = "P94" | PERIOD = 31.25ns | IOSTANDARD = LVCMOS25;

NET Blue(0)     LOC="P99"  | IOSTANDARD=LVTTL;  # B0
NET Blue(1)     LOC="P97"  | IOSTANDARD=LVTTL;  # B1
NET Blue(2)     LOC="P92"  | IOSTANDARD=LVTTL;  # B2
NET Blue(3)     LOC="P87"  | IOSTANDARD=LVTTL;  # B3

NET Green(0)    LOC="P84"  | IOSTANDARD=LVTTL;  # B4
NET Green(1)    LOC="P82"  | IOSTANDARD=LVTTL;  # B5
NET Green(2)    LOC="P80"  | IOSTANDARD=LVTTL;  # B6
NET Green(3)    LOC="P78"  | IOSTANDARD=LVTTL;  # B7

NET Red(0)      LOC="P118" | IOSTANDARD=LVTTL;  # C4
NET Red(1)      LOC="P119" | IOSTANDARD=LVTTL;  # C5
NET Red(2)      LOC="P120" | IOSTANDARD=LVTTL;  # C6
NET Red(3)      LOC="P121" | IOSTANDARD=LVTTL;  # C7

NET vSync       LOC="P116" | IOSTANDARD=LVTTL;  # C2
NET hSync       LOC="P117" | IOSTANDARD=LVTTL;  # C3

ColourTest.vhd

----------------------------------------------------------------------------------
-- Engineer:       Mike Field <hamster@snap.net.nz>
-- Module Name:    ColourTest - Behavioral 
-- Description:    Generates an 800x600 VGA showing all colours
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ColourTest is
    Port ( clk   : in  STD_LOGIC;
           Red   : out  STD_LOGIC_VECTOR (3 downto 0);
           Green : out  STD_LOGIC_VECTOR (3 downto 0);
           Blue  : out  STD_LOGIC_VECTOR (3 downto 0);
           hSync : out  STD_LOGIC;
           vSync : out  STD_LOGIC);
end ColourTest;

architecture Behavioral of ColourTest is
   type reg is record
      hCounter : std_logic_vector(10 downto 0);
      vCounter : std_logic_vector(9 downto 0);

      red      : std_logic_vector(3 downto 0);
      green    : std_logic_vector(3 downto 0);
      blue     : std_logic_vector(3 downto 0);

      hSync    : std_logic;
      vSync    : std_logic;
   end record;
      signal r : reg := ((others=>'0'), (others=>'0'),
                         (others=>'0'), (others=>'0'), (others=>'0'), 
                         '0', '0');
   signal n : reg;
   
   component clk40
   port
   (
      CLK_IN1        : in     std_logic;
      Clk40          : out    std_logic
   );
   end component;

   signal pixelClock : std_logic;
   -- Timing constants
   constant hRez       : natural := 800;
   constant vRez       : natural := 600;

   constant hMaxCount  : natural := 1056;
   constant hStartSync : natural := 840;
   constant hEndSync   : natural := 968;
   constant vMaxCount  : natural := 628;
   constant vStartSync : natural := 601;
   constant vEndSync   : natural := 605;
   
begin
   -- Assign the outputs
   hSync <= r.hSync;
   vSync <= r.vSync;
   Red   <= r.red;
   Green <= r.green;
   Blue  <= r.blue;
   
clockgen : clk40
  port map
   (
    CLK_IN1 => clk,
    Clk40 => pixelClock
   );
    
   process(r,n)
   begin
      n <= r;
      n.hSync <= '0';      
      n.vSync <= '0';      

      -- Count the lines and rows      
      if r.hCounter = hMaxCount-1 then
         n.hCounter <= (others => '0');
         if r.vCounter = vMaxCount-1 then
            n.vCounter <= (others => '0');
         else
            n.vCounter <= r.vCounter+1;
         end if;
      else
         n.hCounter <= r.hCounter+1;
      end if;

      if r.hCounter  < hRez and r.vCounter  < vRez then
         n.red   <= n.hCounter(4 downto 1);
         n.green <= n.hCounter(8 downto 5);
         n.blue  <= n.vCounter(8 downto 5);
      else
         n.red   <= (others => '0');
         n.green <= (others => '0');
         n.blue  <= (others => '0');
      end if;
      
      -- Are we in the hSync pulse?
      if r.hCounter >= hStartSync and r.hCounter < hEndSync then
         n.hSync <= '1';   -- Positive hSync pulse
      end if;

      -- Are we in the vSync pulse?
      if r.vCounter >= vStartSync and r.vCounter < vEndSync then
         n.vSync <= '1'; -- Positive vSync pulse
      end if;
   end process;

   process(pixelClock,n)
   begin
      if rising_edge(pixelClock)
      then
         r <= n;
      end if;
   end process;
end Behavioral;

Personal tools