Solid State Relay

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This FPGA Project was finished in December 2013.

I wanted to drive a Solid State Relay (SSR), which provides a safe way to switch up to 40A at 240V (i.e. lethal power), to work with my reflow oven project. The SSR provides optical isolation from the mains without a lot of work.

To drive the SSR I needed more than 4 volts, so I needed something to convert the 3.3V logic to 5V levels.

Ssr driver schematic.jpg

Although the back-of-a-business-card design looks pretty random, there is at least a little bit of thinking in there. The upper resistor limits the fault current through the SSR outputs to 50mA, the middle one limits current into the transistor's base to about 10mA, and the lower one is to prevent a soft pull-up (such as occurs during FPGA config) from turning the mains on - a drive impedance of around 1k0 Ohm or less is needed to get the transistor's base above 0.6V, allowing the transistor to turn on.

I made a custom 'wing' just using strip board, pin headers and a few bits of junk (I think I have had that transistor in my junk box for 20 years). The board pretty much follows the schematic:

Ssr driver.jpg

And here is the extension cable with the SSR spiced into the phase wire. To make it safe all exposed contacts and primary insulation (green, blue, brown) has to be covered in insulation tape.

Ssr cable 1.jpg Ssr cable 2.jpg

You can see it in action at http://youtu.be/cJHiEr5BYqY


ssr_test.vhd

This is a very, very short test program - to generate a 25% duty cycle signal at about 0.25Hz.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ssr_test is
    Port ( clk : in  STD_LOGIC;
           ssr_enable : out  STD_LOGIC);
end ssr_test;

architecture Behavioral of ssr_test is
   signal counter : unsigned(26 downto 0) := (others => '0');
begin
   
process(clk)
   begin
      if rising_edge(clk) then
         ssr_enable <= counter(counter'high) and counter(counter'high-1); -- on with 75% duty cycle at 
         counter <= counter+1;
      end if;
   end process;

end Behavioral;

ssr_test.ucf

NET CLK         LOC="P89"  | IOSTANDARD=LVTTL | PERIOD=31.25ns;               
NET ssr_enable  LOC="P9"  | IOSTANDARD=LVTTL; 

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