Spdif output.vhd

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S/PDIF output serialiser for the SPDIF_Thru FPGA project.

----------------------------------------------------------------------------------
-- Engineer: Mike Field (hamster@snap.net.nz)
-- 
-- Create Date:    16:34:46 09/04/2011 
-- Module Name:    spdif_out - Behavioral 
--
-- Description: Takes the frames and sends them out one bit at a time...
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity spdif_out is
    Port ( clock100 : in  STD_LOGIC;
           bitclock : in  STD_LOGIC;
           newSubframe : out std_logic;
           
           subframe     : in  STD_LOGIC_VECTOR (27 downto 0);
           channelA     : in  STD_LOGIC;
           startOfFrame : in  STD_LOGIC;
           
           spdif_out : out  STD_LOGIC);
end spdif_out;

architecture Behavioral of spdif_out is
   type reg is record
      current   : std_logic;
      newSubframe: std_logic;
      bits      : std_logic_vector(63 downto 0);
      bitcount  : std_logic_vector(5 downto 0);
   end record;
   
   signal r : reg := ('0', '0', (others => '0'), (others => '0'));
   signal n : reg;
   
   signal parity         : std_logic;
   signal auxAudioBits   : std_logic_vector(3 downto 0);
   signal sample         : std_logic_vector(19 downto 0);
   signal subcode         : std_logic;
   signal validity      : std_logic;
   signal channelStatus   : std_logic;
   signal preamble       : std_logic_vector(7 downto 0);

   
begin
   spdif_out      <= r.current;
   newSubframe   <= r.newSubframe;
   
   channelStatus <= subframe(26);
   subcode       <= subframe(25);
   validity      <= subframe(24);
   sample        <= subframe(23 downto 4);
   auxAudioBits  <= subframe(3 downto 0);

   parity <= auxAudioBits(3) xor auxAudioBits(2) xor auxAudioBits(1) xor auxAudioBits(0) xor
             sample(19)       xor sample(18)      xor sample(17)      xor sample(16)      xor
             sample(15)       xor sample(14)      xor sample(13)      xor sample(12)      xor
             sample(11)       xor sample(10)      xor sample(9)       xor sample(8)       xor
             sample(7)        xor sample(6)       xor sample(5)       xor sample(4)       xor
             sample(3)        xor sample(2)       xor sample(1)       xor sample(0)       xor 
             subcode          xor validity        xor channelStatus   xor '0';

   process (channelA,startOfFrame)
   begin
      if channelA = '1' then
         if startOfFrame = '1' then
            preamble <= "00111001"; -- M preamble - Channel A, Start of Frame
         else
            preamble <= "11001001"; -- Y preamble - Channel A, middle of Frame
         end if;
      else
         preamble <= "01101001"; -- Z preamble - other channel
      end if;
   end process;



   process(r, bitclock, preamble, channelStatus, validity, subcode, auxAudioBits, sample, parity)
   begin
      n <= r;
      n.newSubframe <= '0';
      if bitclock = '1' then 
         n.current <= r.current xor r.bits(0) xor '0';
         if r.bitCount = "111111" then
            n.newSubframe <= '1';
            n.bits <= parity     & "1" & channelStatus   & "1" & subcode         & "1" & validity        & "1" & 
                  sample(19)      & "1" & sample(18)      & "1" & sample(17)      & "1" & sample(16)      & "1" &
                  sample(15)      & "1" & sample(14)      & "1" & sample(13)      & "1" & sample(12)      & "1" & 
                  sample(11)      & "1" & sample(10)      & "1" & sample( 9)      & "1" & sample( 8)      & "1" & 
                  sample( 7)      & "1" & sample( 6)      & "1" & sample( 5)      & "1" & sample( 4)      & "1" & 
                  sample( 3)      & "1" & sample( 2)      & "1" & sample( 1)      & "1" & sample( 0)      & "1" & 
                  auxAudioBits(3) & "1" & auxAudioBits(2) & "1" & auxAudioBits(1) & "1" & auxAudioBits(0) & "1" & 
                  preamble;
         else
            n.bits <= "0" & r.bits(63 downto 1);
         end if;
         n.bitCount <= r.bitcount +1;
      end if;
   end process;
   
   process(clock100,n)
   begin
      if rising_edge(clock100) then
         r <= n;
      end if;
   end process;
end Behavioral;




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