Spdif thru.vhd

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Top level for the SPDIF_Thru FPGA project.

----------------------------------------------------------------------------------
-- Engineer: Mike Field (hamster@snap.net.nz
-- 
-- Create Date:    16:21:41 09/04/2011 
-- Module Name:    spdif_thru - Behavioral 
--
-- Description: Top level of the spdif_thru project
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity spdif_thru is
    Port ( clock50  : in  STD_LOGIC;
           spdif_rx : in  STD_LOGIC;
           spdif_tx : out  STD_LOGIC;
           led        : out  STD_LOGIC_VECTOR(7 downto 0));
end spdif_thru;

architecture Behavioral of spdif_thru is
   COMPONENT clock50to100
   PORT(
      CLKIN_IN : IN std_logic;          
      CLKIN_IBUFG_OUT : OUT std_logic;
      CLK0_OUT : OUT std_logic;
      CLK2X_OUT : OUT std_logic
      );
   END COMPONENT;

   COMPONENT spdif_in
   PORT(
      clock100     : IN std_logic;
      spdif_in     : IN std_logic;          
      sampleNow    : IN std_logic;          
      subframe     : OUT std_logic_vector(27 downto 0);
      startOfFrame : OUT std_logic;
      channelA     : OUT std_logic;
      newSubframe  : OUT std_logic;
      transition   : OUT std_logic
      );
   END COMPONENT;

   COMPONENT clock_recovery
   PORT(
      clock100   : IN  std_logic;
      transition : IN  std_logic;          
      sampleNow  : OUT std_logic
      );
   END COMPONENT;

   COMPONENT sample_fifo
   PORT (
    clk : IN STD_LOGIC;
    din : IN STD_LOGIC_VECTOR(29 DOWNTO 0);
    wr_en : IN STD_LOGIC;
    rd_en : IN STD_LOGIC;
    dout : OUT STD_LOGIC_VECTOR(29 DOWNTO 0);
    full : OUT STD_LOGIC;
    empty : OUT STD_LOGIC;
    underflow : OUT STD_LOGIC;
    data_count : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
   );
   END COMPONENT;

   COMPONENT spdif_out
   PORT(
      clock100       : IN std_logic;
      bitclock       : IN std_logic;
      subframe       : IN std_logic_vector(27 downto 0);
      channelA         : IN std_logic;          
      startOfFrame    : IN std_logic;          
      
      newSubFrame      : OUT std_logic;          
      spdif_out       : OUT std_logic
      );
   END COMPONENT;

   COMPONENT fractional_clock
   PORT(
      clock100 : IN std_logic;
      adj_quicker_lots : IN std_logic;
      adj_quicker : IN std_logic;
      adj_slower : IN std_logic;
      adj_slower_lots : IN std_logic;          
      ce_out : OUT std_logic
      );
   END COMPONENT;

   COMPONENT data_rate_matcher
   PORT(
      clock100 : IN std_logic;
      data_count : IN std_logic_vector(8 downto 0);          
      adj_quicker_lots : OUT std_logic;
      adj_quicker : OUT std_logic;
      adj_slower : OUT std_logic;
      adj_slower_lots : OUT std_logic
      );
   END COMPONENT;
   
   signal sampleNow           : std_logic;
   signal inputTransition     : std_logic;
   signal fifoEmpty           : std_logic;
   
   signal inputSubframe      : std_logic_vector(27 downto 0);
   signal inputChannelA      : std_logic;
   signal inputStartOfFrame  : std_logic;
   signal inputNewSubframe   : std_logic;

   signal outputSubframe     : std_logic_vector(27 downto 0);
   signal outputChannelA     : std_logic;
   signal outputStartOfFrame : std_logic;
   signal outputNewSubframe  : std_logic;

   signal fifoInput          : std_logic_vector(29 downto 0);
   signal fifoOutput         : std_logic_vector(29 downto 0);
   
   signal dataCount             : std_logic_vector(8 downto 0);
   signal clock100          : std_logic;
   signal bitclock          : std_logic;
   signal adj_ql             : std_logic;
   signal adj_q             : std_logic;
   signal adj_s             : std_logic;
   signal adj_sl             : std_logic;

begin
   led <= dataCount(8 downto 1);
   
   -- Scatter/gather the singals for the FIFO data
   fifoInput <= inputStartOfFrame &   inputChannelA & inputSubframe;
   outputStartOfFrame <= fifoOutput(29);
   outputChannelA     <= fifoOutput(28);
   outputSubframe     <= fifoOutput(27 downto 0);
   
   
clock_doubler: clock50to100 PORT MAP(
      CLKIN_IN          => Clock50,
      CLKIN_IBUFG_OUT   => open,
      CLK0_OUT          => open,
      CLK2X_OUT          => Clock100
   );


spdif_input: spdif_in PORT MAP(
      clock100      => clock100,
      spdif_in      => spdif_rx,
      sampleNow     => sampleNow,
      subframe      => inputSubframe,
      startOfFrame  => inputStartOfFrame,
      channelA      => inputChannelA,
      newSubframe   => inputNewSubframe,
      transition    => inputTransition
   );

recover_clock: clock_recovery PORT MAP(
      clock100   => clock100,
      transition => inputTransition,
      sampleNow  => sampleNow
   );
   

sample_store : sample_fifo
  PORT MAP (
    clk          => clock100,
    din          => fifoInput,
    wr_en       => inputNewSubframe,
    rd_en       => outputNewSubframe,
    dout       => fifoOutput,
    full       => open,
    empty       => fifoEmpty,
    underflow    => open,
    data_count => dataCount
  );

   spdif_output: spdif_out PORT MAP(
      clock100     => clock100,
      bitclock      => bitclock,
      spdif_out     => spdif_tx,
      subframe     => outputSubframe,
      channelA       => outputChannelA,
      startOfFrame => outputStartOfFrame,
      newSubFrame  => outputNewSubframe
   );
   
gen_bit_clock: fractional_clock PORT MAP(
      clock100          => clock100,
      ce_out             => bitclock,
      adj_quicker_lots   => adj_ql,
      adj_quicker       => adj_q,
      adj_slower          => adj_s,
      adj_slower_lots    => adj_sl
   );

rate_matcher: data_rate_matcher PORT MAP(
      clock100         => clock100,
      data_count       => datacount,
      adj_quicker_lots => adj_ql,
      adj_quicker      => adj_q,
      adj_slower         => adj_s,
      adj_slower_lots  => adj_sl
   );

end Behavioral;

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