Terasic DE0-nano

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The DE0-nano is a very small FPGA development board from Terasic (http://www.terasic.com.tw/).

It has a Cyclone IV Gate Array, SDRAM and SPI Flash, and a few useful switches, LEDs and buttons.

File:De0-nano.jpg

It is not an idea development board for experimenting with, but due to the amount of SDRAM and flash it is an excellent platform for System on a Programmable Chip (SoPC) projects.

Contents

Full list of features

  • Altera Cyclone IV EP4CE22F17C6N FPGA
    • 22,320 Logic elements (LEs)
    • 594Kbits embedded memory
    • 66 Embedded 18 x 18 multipliers (which can also be 132 9x9 multipliers)
    • 4 General-purpose PLLs
  • On-board USB-Blaster circuit for programming
  • Altera serial configuration device – EPCS16
  • Two 40-pin Headers (GPIOs) provides 72 I/O pins
  • Two 5V power pins, two 3.3V power pins and four ground pins
  • One 26-pin header provides 16 digital I/O pins and 8 analog input pins to connect to analog sensors, etc
  • ISSI IS42S16160B-7 32MB SDRAM (16Mx16 bit words)
  • 2Kb I2C EEPROM
  • 8 green LEDs
  • 2 debounced push-buttons
  • 4 dip switches
  • ADI ADXL345, 3-axis accelerometer with high resolution (13-bit)
  • NS ADC128S022, 8-Channel, 12-bit A/D Converter
  • On-board 50MHz clock oscillator
  • USB Type mini-AB port (5V supply)
  • Two DC 5V pins of the GPIO headers (5V)
  • 2-pin external power header (3.6-5.7V)

Datasheets for components

Here is a collection of datasheets I have found useful.

A note on the configuration flash

The EPCS16 holds 16 megabits, (or 2 megabytes). The FPGA only needs 688 kilobytes for it's configuration, leaving about 1.3 megabytes free for holding user data.

This can be accessed in a method similar to http://papilio.cc/index.php?n=Playground.Bootstrap

NIOS II

Like Microblaze on Xilinx FPGAs, Altera have a preferred 'soft' 32 bit CPU called NIOS II. An extensive toolset has been developed around this, allowing rapid design and implementation of a SOPC system.

Here is the basic design flow for the DE0-nano:

  • Use then DE0-nano system builder tool to configure your external interfaces and create a Quartus II project
  • Open the project in Quartus, then launch Qsys.
    • Select your components (processor, UART, memory...)
    • Click with a mouse to join the wires and buses
    • Define the system memory map
    • Generate the design
  • Back in Quartus add the generated design in your project.
  • Use the HDL template from qsys to add the system to the top-level Verilog file, and then connect it to the outside world
  • Compile and implement the design for the FPGA,
  • Start the Eclipse to work on the software side of the project.
    • Use the BSP builder to build the support library for your design
    • Use Eclipse to write and compile your C application
  • Download the hardware design to the FPGA
  • Download the memory image / 'elf' file to the NIOS II's system's memory over JTAG
  • Enjoy!

ucLinux on NIOS II

I've booted ucLinux on the DE0-nano, and am working on building a uClinux for DE0 on Fedora 14.


If anybody is using Windows, and want to get it up and running real quick using a prebuilt configuration. Download 'DE0-nano.sof' and 'zImage' from http://www.ccm.ece.vt.edu/usvn/svn/alteraApps/trunk/uClinux/precompiled/DE0-Nano/ Launch "Nios II 11.0sp1 Command Shell" (or equivalent version)

bash-3.1$ nios2-configure-sof /cygdrive/c/Users/<username>/Downloads/DE0_Nano.sof
...
bash-3.1$ nios2-download -g /cygdrive/c/Users/<username>/Downloads/zImage
...
bash-3.1$ nios2-terminal.sh
nios2-terminal: connected to hardware target using JTAG UART on cable
nios2-terminal: "USB-Blaster [USB-0]", device 1, instance 0
nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)

Uncompressing Linux... Ok, booting the kernel.
Linux version 2.6.30 (tannous@ccm14) (gcc version 3.4.6) #2 PREEMPT Tue Mar 29 1
3:33:35 EDT 2011


uClinux/Nios II
Built 1 zonelists in Zone order, mobility grouping off.  Total pages: 8128
Kernel command line:
NR_IRQS:32
PID hash table entries: 128 (order: 7, 512 bytes)
Dentry cache hash table entries: 4096 (order: 2, 16384 bytes)
Inode-cache hash table entries: 2048 (order: 1, 8192 bytes)
Memory available: 30812k/1659k RAM, 0k/0k ROM (937k kernel code, 722k data)
Calibrating delay loop... 48.94 BogoMIPS (lpj=244736)
Mount-cache hash table entries: 512
init_BSP(): registering device resources
bio: create slab <bio-0> at 0
io scheduler noop registered
io scheduler deadline registered (default)
ttyJ0 at MMIO 0x4001030 (irq = 1) is a Altera JTAG UART
console [ttyJ0] enabled
Freeing unused kernel memory: 576k freed (0x210e000 - 0x219d000)
Shell invoked to run file: /etc/rc
Command: hostname uClinux
Command: mount -t proc proc /proc -o noexec,nosuid,nodev
Command: mount -t sysfs sysfs /sys -o noexec,nosuid,nodev
Command: mount -t devpts devpts /dev/pts -o noexec,nosuid
Command: mount -t usbfs none /proc/bus/usb
mount: mounting none on /proc/bus/usb failed: No such file or directory
Command: mkdir /var/tmp
Command: mkdir /var/log
Command: mkdir /var/run
Command: mkdir /var/lock
Command: mkdir /var/empty
Command: ifconfig lo 127.0.0.1
ifconfig: socket: Function not implemented
Command: route add -net 127.0.0.0 netmask 255.0.0.0 lo
route: socket: Function not implemented
Command: cat /etc/motd
Welcome to
          ____ _  _
         /  __| ||_|
    _   _| |  | | _ ____  _   _  _  _
   | | | | |  | || |  _ \| | | |\ \/ /
   | |_| | |__| || | | | | |_| |/    \
   |  ___\____|_||_|_| |_|\____|\_/\_/
   | |
   |_|

For further information check:
http://www.uclinux.org/

Execution Finished, Exiting

Sash command shell (version 1.1.1)
/>

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