TinyTx

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This small FPGA Project was completed in July 2016.

A thread on EEVBlog had me thinking about the smallest amount of code and logic to send bytes out of a serial port, and here it is. The TX code needs 12 LUTs and 11 flip-flops.

Contents

Source

tiny_rs232_tx.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tiny_rs232_tx is
    Port ( clk         : in  STD_LOGIC;
           bit_tick    : in  STD_LOGIC;
           data        : in  STD_LOGIC_VECTOR(7 downto 0);
           data_enable : in  STD_LOGIC;
           tx          : out STD_LOGIC := '1';
           busy        : out STD_LOGIC );
end tiny_rs232_tx;

architecture Behavioral of tiny_rs232_tx is
    signal shift_reg  : std_logic_vector(9 downto 0) := (others => '1');
    signal i_busy     : std_logic;
begin
    busy <= i_busy;
    with shift_reg select i_busy <= '0' when "0000000000", '1' when others;

clk_proc: process(clk)
    begin
        if rising_edge(clk) then
            if i_busy = '0' and data_enable = '1' then
                shift_reg <= '1' & data & '0';
            end if;             
        
            if bit_tick = '1' then
                if i_busy = '1' then
                    tx <= shift_reg(0);
                    shift_reg <= '0' & shift_reg(9 downto 1);
                end if;
            end if;
        end if;
    end process;
end Behavioral;

basys3.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity basys3 is
    Port ( clk  : in STD_LOGIC;
           sw   : in STD_LOGIC_VECTOR (7 downto 0);
           btnC : in STD_LOGIC;
           RsTx : out STD_LOGIC;
           led  : out STD_LOGIC_VECTOR (7 downto 0) := (others => '1'));
end basys3;

architecture Behavioral of basys3 is
    component tiny_rs232_tx is
    Port ( clk         : in  STD_LOGIC;
           data        : in  STD_LOGIC_VECTOR(7 downto 0);
           data_enable : in  STD_LOGIC;
           bit_tick    : in  STD_LOGIC;
           tx          : out STD_LOGIC := '1';
           busy        : out STD_LOGIC);
    end component;
    signal count      : unsigned(12 downto 0)        := (others => '1');
    signal bit_tick   : std_logic := '0';
begin
    with count select bit_tick <= '1' when "0000000000000", '0' when others;

process(clk) 
    begin
        if rising_edge(clk) then
            if count = 100_000_000/19_200-1 then
                count <= (others => '0');
            else
                count <= count +1;
            end if;
        end if;
    end process;

i_tiny_rs232_tx: tiny_rs232_tx port map (
    clk         => clk,
    data        => sw,
    data_enable => btnC,
    bit_tick    => bit_tick,
    tx          => RsTx,
    busy        => led(0));

end Behavioral;

basys3.xdc

set_property PACKAGE_PIN W5 [get_ports clk]							
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
 
## Switches
set_property PACKAGE_PIN V17 [get_ports {sw[0]}]					
set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
set_property PACKAGE_PIN V16 [get_ports {sw[1]}]					
set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
set_property PACKAGE_PIN W16 [get_ports {sw[2]}]					
set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
set_property PACKAGE_PIN W17 [get_ports {sw[3]}]					
set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
set_property PACKAGE_PIN W15 [get_ports {sw[4]}]					
set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
set_property PACKAGE_PIN V15 [get_ports {sw[5]}]					
set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
set_property PACKAGE_PIN W14 [get_ports {sw[6]}]					
set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
set_property PACKAGE_PIN W13 [get_ports {sw[7]}]					
set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]

## LEDs
set_property PACKAGE_PIN U16 [get_ports {led[0]}]					
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property PACKAGE_PIN E19 [get_ports {led[1]}]					
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property PACKAGE_PIN U19 [get_ports {led[2]}]					
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property PACKAGE_PIN V19 [get_ports {led[3]}]					
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property PACKAGE_PIN W18 [get_ports {led[4]}]					
set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
set_property PACKAGE_PIN U15 [get_ports {led[5]}]					
set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
set_property PACKAGE_PIN U14 [get_ports {led[6]}]					
set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
set_property PACKAGE_PIN V14 [get_ports {led[7]}]					
set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]

##Buttons
set_property PACKAGE_PIN U18 [get_ports btnC]						
set_property IOSTANDARD LVCMOS33 [get_ports btnC]

##USB-RS232 Interface
set_property PACKAGE_PIN A18 [get_ports RsTx]						
	set_property IOSTANDARD LVCMOS33 [get_ports RsTx]

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