Zedboard VGA HDMI
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This FPGA Project was finished in September 2013, then improved, and then tinkered with a bit more. And then I added 1080p. I guess it might never be finished...
After getting the HDMI converter displaying colours using YCbCr data (see Zedboard HDMI v2, the next step is to allow it to display RGB 444 data by implementing colour space and pixel format conversion. Here is the test pattern displaying on the HDMI port (I set the transmitter to use DVI signalling, so it isn't actually HDMI):
Comparison with VGA port
Here is what is also being sent by the analogue VGA port - which can only display 12-bit colours:
And this is the DVI signal over the HDMI port:
An early attempt
This is the project files for an early version with just vertical colour bars
This first solution below is sub-optimal - by using the chaining options in the DSP blocks this could be implemented with far fewer registers, however that would require a lot of Xilinx specific code and design work. Currently the only Xilinx specific code is the IP for a multiplier for unsigned 9-bit and signed 16-bit numbers.
The clocking is also a little odd. I've used the pixel clock, shifted 90 degrees, to drive the DDR output that generates the forwarded HDMI_CLK signal. This is reliable solution, but is not very efficient on clocking resources. By playing with the settings in register D0 it should be possible to remove this clock domain.
I've also included a module called clamper. It is not needed in the pipeline as the maths used will not generate values that are out of range (16 to 239 for CbCr, 16 to 235 for Y). This could be removed completely (in fact if it is used Cb & Cr are being clamped into the 16 to 235 range, in error).
I used the internal registers of the DSP48E1 to minimise resources used for colour conversion, and to also maximize performance. The original version would fail timing when I attempted 1080p as the outputs of all three multipliers are added in one cycle. The DSP blocks have internal registers, adders and cascade ports that can be used instead of the CLBs in the FPGA fabric.
For the latest version I now have an Fmax of 196MHz (when constrained for 150MHz). Because I am using primitives this version needs no IP blocks outside of the VHDL sources. The downside is that the colour conversion module is well over 500 lines long.
Current usage is 84 slices (316 registers, 223 LUTs, 3 LUTRAM) and 6 DSP blocks). 16 of the slices are used to generate the test pattern. This is less than 1% of the Zynq's logic, and less than 2% of the 220 DSP48E1 blocks.
For 1080p the data rate is quite high (3.3Gb/s as it is a 11-bit wide DDR interface running at 150MHz). I had lots of problems getting the relative phase of the HDMI clock correct, and even then it will only work with the FAST attribute on the output registers. When you get this wrong the Intensity and chroma components can get all mixed up, causing it to look like this:
If you see something like this it can be a timing problem, not a code / logic problem. Double check your constraints, try tweaking the phase of the HDMI clock, and always ensure that you configure a fully reset board (as I don't reset all of the transmitter's registers, only those needed to bring up the transmitter from a power-on reset).
Final project files
File:Zed vga hdmi 720p.zip - version to display 720p images (720p @ 60Hz)
File:Zed vga hdmi 1080p.zip - version to display 1080p images. Timing is very sensitive to drive speed and relative clock phase, and found by trial and error. I would love to here if this works for you (and help debug if it doesn't.
VERY IMPORTANT NOTE
The ADV7511 will reset some registers if the HDMI cable is hot-plugged. I don't detect this or allow for it. Make sure that you HDMI cable is plugged in before you power your board up, and don't expect it to work if you unplug the cable or power the monitor off.
As well as Wikipedia;s article on YCbCr (http://en.wikipedia.org/wiki/YCbCr), the following PDF is a good reference: http://compression.ru/download/articles/color_space/ch03.pdf