DSPfract old mem
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Old notes for the memory controller for DSPfract project Here are the memory cycles (all of this is work in progress)
Read from address
This is using "Read Cycle No. 1" from the data sheet:
|1||Z + latch|
Write to address
I'm crossing fingers that I can latch the data bus at the start of write cycle - but it is pretty aggressive to do:
process(...) ... latch_data <= mem_data; mem_data <= data_to_write; ... end process
If this won't work I might need to insert an IDELAY2 to delay the signal a little - I hope that I don't have to!
This is using "Write Cycle #2 - nWE controlled, nOE high during write" from the data sheet.
( the signals with two values are using DDR signalling on nWE)
It might be that data needs to be presented for all of cycle 2, in which case all consecutive wrotes will need to be followed by an idle cycle.
nWR will be driven by an ODDR2 primitive to enable the the WR signal to be driven for two half a cycles.
|0||1||0||1||0||0||Read Address||Z (possible latch from prior read)|
Using a 10ns cycle, we can read 200MB/sec or write 100MB/sec. States are such that Read and writes can be stacked in any order without idle states between.
Integrating with video memory requirements
I'm planning to run everything outside of the calculation core at 100MHz. With the display running at 800x600 with a 50MHz pixel clock (see http://tinyvga.com/vga-timing/800x600@72Hz) requires one byte every 2 cycles - one 16 bit word read every four cycles.
Memory access pattern 1
The pattern should work:
- read cycle 0
- write cycle 0 / idle cycle if no write pending
- write cycle 1 / idle cycle if no write pending
- idle cycle
It reads 50MB/sec, but as I am using single byte writes it only allows 25MB/sec to be written - still far better than my Nexys2 version's 7MB/sec. The read cycle is only needed during the active part of the display, so maybe I could run back to back cycles during the blanking intervals, boasting writes to 50MB/sec. Top throughput will then be 69.12% at 25MB/s and 30.88% at 50MB/sec = 32.72MB/s
Memory access pattern 2
The pattern improves performance:
- read #1 cycle 0
- read #2 cycle 0
- write #1 cycle 0
- write #1 cycle 1
- write #2 cycle 0
- write #2 cycle 1
- write #3 cycle 0
- write #3 cycle 1
It still reads 50MB/sec, but writes are improved by 50% to 37.5MB/s because it avoids the idle cycle. If continuous writes are used during the blanking intervals the throughput will then be 69.12% at 37.5MB/s and 30.88% at 50MB/sec = 42.86MB/s