FPGA Projects

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! Project !! Description!! Status
! Project !! Description!! Status
| [[Arbiter]] || A high performance 4-input arbiter for LTU-6 architectures || Completed
| [[CORDIC complex magnitude]] || Calculate the magnitude of I+Q values || Completed
| [[CORDIC complex magnitude]] || Calculate the magnitude of I+Q values || Completed

Latest revision as of 09:39, 6 October 2019

Projects I've been playing with that use Field Programmable Gate Arrays, and their status

Sorry for the slow updates - life is getting in the way of my hobbies, but I am working on a big project...

Project Description Status
Arbiter A high performance 4-input arbiter for LTU-6 architectures Completed
CORDIC complex magnitude Calculate the magnitude of I+Q values Completed
Hilbert Transform Converting a real signal, into a complex analytic signal Completed
GPSDO A (very poor) GPS Disciplined 1MHz oscillator Completed
CORDIC Calculating SIN() and COS using only addition and bit shifts Completed
HDMI header error correction One of the error checking and correcting codes used in HDMI Completed
High_performance_FIR A high performance FIR filter for Spartan 6 Completed
DigitalClock Working on a design for a digital clock Completed
STGL5000 Configuring the SGTL5000 low-power audio codec Completed
Combination Lock A four-digit combination lock for the Basys-3 Completed
MMCM_reset Dynamically reconfigure the 7-series MMCM block Completed
Simple AXI Slave An AXI slave for Zynq's ARM CPUs Completed
myStorm Blackice First project with an Open Source FPGA toolset Completed
TinyTx Making a really tiny serial TX Completed
GigabitTX Sending data from a 10/100/1000 Ethernet Port Completed
ArtyEthernet Sending data on the Digilent Arty's 10/100 Ethernet Port Completed
Morse Transmit Morse code with the Arty Completed
Synchronizer The right way to synchronize an input signal Completed
MIC and AMP Adding a Microphone to the PMODamp3 design Completed
PMODamp3 Driving an Class D I2S power amp module Completed
Virtual IO Using the Vivado Debug Virtual IP Completed
MPU6050 sensor RTL Using a Gyro / Acceleration / Attitude sensor directly in RTL Completed
Single Step A way to allow switching to a single-step clock in Spartan 6 Completed
XADC Fan PWM Using the 7-series XADC to control fan speed Completed
Minimal XADC design Reading an input from the on-FPGA ADX on the Basys3 Completed
Better rotary encoder input My early attempt at quadrature decoding wasn't that good Completed
Genesys2 Mandelbrot Port of the Artix-7 Fractal viewer to the Kintex-7 on the Genesys2 Completed
DisplayPort A DisplayPort interface Completed
HDMI Capture Capturing HDMI data and sending it to the serial port Completed
HDMI Processing HDMI Video and Audio extraction on an Artix 7 board Completed
EDID ROM An basic EDID for a video project Completed
SERDES symbol locking How to find a working bitslip / input delay setting for 7-series ISERDES Completed
Artix 7 1080p passthrough Passing HDMI signals through the Nexys Video Completed
Square root Calculating the integer square root of a number Completed
Artix 7 1080p Seeing if the Artix-7 can generate 1080p, with a little over-clocking Completed
Mandelbrot NG 1080i A full-HD on the fly Mandelbrot Fractal viewer for the Nexys Video Completed
GPS Spew A desktop GPS jammer Completed
OSERDESE2 An example 10:1 serialiser that simulates properly Completed
Digital Microphone Getting data from a PmodMIC3 - A MEM Smicrophone and 12-bit ADC Completed
Mandelbrot NG A new real time Mandelbrot viewer Completed
Ring Oscillator Creating a ring oscillator in an FPGA Completed
Digital Sine Creating relatively accurate analog sine waves with an DAC Completed
PmodAD1 Reading an analog joystick with the PmodAD1 (Analog Devices AD7476 ADC) Completed
FPGA_ESP8266 Interfacing your FPGA to wifi using low cost ESP8266 module Completed
PmodMAXSONAR Using the serial interface on the PmodMAXSONAR module Completed
Minimal HDMI A super-light-weight 3 bits per pixel true HDMI interface Completed
Minimal DVI-D A super-light-weight 9 bits per pixel DVI-D interface Completed
Log Pins A tiny project to send the start of 11 pins to a host over RS232 Completed
miniSpartan6+ SPI Programming Writing your logic design into the board's SPI configuration FLASH Completed
miniSpartan6+ DVID Logo Overlaying the Hamsterworks Logo on a DVI-D stream Completed
miniSpartan6+ Audio Playing beeps In progress
miniSpartan6+ DVID Output A better DVI-D output for the Scarab Hardware miniSpartan6+ board Completed
miniSpartan6+ bringup First bringup of the Scarab Hardware miniSpartan6+ board Completed
Stepper Controlling a small stepper motor Completed
Math free digital clock A digital clock that doesn't know how to add! Completed
LFSR Divider Using a LFSR to divide a clock signal Completed
Sonar Interfacing a low-cost sonar module to an FPGA Completed
Simple resets don't work Showing how not to implement a reset Completed
DDS via a VGA port Analysing how well a VGA port can generate a 6.25 MHz frequency sine wave Completed
Inferred FIFO Implementing a FIFO to avoid using IP Completed
Cheap Analogue Input Reading an analogue joystick without a ADC Completed
HDMI Input Receiving high-speed digital video (DVI-D over HDMI) Completed
Intelligent LEDs Driving Intelligent LEDs Completed
SDRAM Audio playback Playing back extended audio from SDRAM Completed
FPGA wheelchair fairy lights LED lights for my boy's wheelchair Completed
Accessing the configuration clock Using the internal oscillator Completed
High Speed Frequency Counter Counting the fastest of clocks Completed
DVI-D Serdes Creating a DVI-D signal using the OSERDES2 Serializers Completed
SD card testing Playing around with the SPI interface on an SD card Completed
Logic Analyser Test An 8-bit 200MHz counter to test a Logic Analyser Completed
Eternity2 Solver Using an FPGA to solve the Eternity II puzzle Completed
Zedboard Audio Using the I2S Audio codec on the Zedboard from VHDL Completed
Reflow Oven Solder reflow using an benchtop oven and a FPGA Completed
FIR Filter Implementing a FIR filter in an FPGA Completed
Solid State Relay Driving a SSR from the a FPGA Completed
Analog Wing Using the Papilio Analogue Wing Completed
Thermocouple demo Capturing data using a Adafruit Thermocouple interface Completed
Simple SDRAM Controller A very simple SDRAM controller Completed
Zedboard_VGA_HDMI Driving the Zedboard's VGA and HDMI interface, at one clock per Pixel

Includes RGB444 to YCbCr conversion

Zedboard_HDMI_v2 Driving the Zedboard's HDMI interface Completed
pmodi2s Driving a Digilent PMODI2S Audio DAC Completed
pmodenc Decoding the input from the Digitent PMODENC rotary encoder Completed
mains_hum_filter A low-pass DSP filter removing 50Hz hum from an ADC's samples Completed
a2d_graph Slowly graphing channel 0 on the LogicStart's ADC Completed
DSP_Filter_Design Various bits and bobs for FIR filter design Completed
I3C2 An Intelligent I2C Controller Completed
Audio filter Simulating a passive analogue audio filter Planning
Dualhead MCB Frame Buffer Adding a DVI-D output to the MCB Frame Buffer Completed
MCB Frame Buffer Creating a 720p frame buffer in the Pipistrello's LPDDR memory Completed
USB TTL RS232 Using the Papilio as a TTL RS232 adapter Completed
Spartan 6 1080p Generating 1080p on a Spartan 6 LX Completed
High Speed Link High speed transfer between two FPGAs Completed
RS232_dumper Capture then dump data to the RS232 port Completed
Zedboard_HDMI Driving the Zedboard's HDMI interface In Development
Zedboard_OV7670 Attaching a low cost camera to the Zedboard Completed
Async_VGA A VGA Controller that works with bursts of data (e.g. from SDRAM) Completed
FreqSwitch CHanging a DCM_CLKGEN's output "on the fly" to generate different frequencies Completed
FM_SOS Send SOS with a simple FM transmitter Completed
OV7670_camera Video capture from a cheap camera module Completed
Digilent EPP Performance Performance difference in the EPP port speed on digilent boards Completed
OSERDES2 clocking Setting up the clocking infrastructure for high speed serial output Untested
frequency_counter GPS referenced frequency counter Completed
hidef_snow Generate static in 1080p Completed
config_flash Storing arbitrary data in the configuration flash Completed
async_reset Testing async reset reliability Completed
meta_test Testing for metastability Completed
if vs case Testing different implementations Completed
ray_cast A "ray casting" 3D maze walk through In Progress
dx_display Driving a Deal Extreme TM1638 7 Seg Display Completed
Synth A simple all-digital Synth, in bite sized parts Partially complete
Crystal Castles Reimplementing the old arcade machine on an FPGA In progress
CheapScope A simple fabric embedded logic analyser, with and RS232 interface Completed
dvid_test Driving a DVI-D interface from a Spartan 6 FPGA Completed
HDlife Implementing Conway's Game of Life at full HD Completed
FPGAheli Controlling an Infrared Helicopter Completed
shortwave A very quick and dirty shortwave transmitter Completed
AVR8 core An AVR103 nearly compatible soft core originally from OpenCores Running, but no documentation yet.
10BaseT-TX Sending out Ethernet packets directly from the FPGA Completed
SPDIF_Input Capturing and converting digital audio data from DVD players Completed
SPDIF_out Generating digital audio data output Completed
SPDIF_Volume A simple digital volume control for a S/PDIF signal - a very simple DSP Completed
SPDIF_Thru A passthrough for S/PDIF singal - a base for DSP projects Completed
VGA Display Generating the timings for 1440x900 VGA output Completed
WavePlay Playing 8bit stereo audio samples from Block RAM Completed
Mandelbrot Yet another FPGA Mandelbrot viewer Completed
DSPfract Yet another FPGA Mandelbrot viewer - this time using Spartan 6 DSP48A bocks Completed
Radix2div Radix 2 division in VHDL Completed
Radix4div Radix 4 division in VHDL Abandoned
SDRAM Memory Controller Memory controller for the SDRAM chip on the Terasic DE0-nano Design complete, implementation mostly complete. Testing to start.
uClinux Bringing up uClinux on a Terasic DE0-nano board Completed
MAF6502 A FPGA implementation of the classic MOS6502 processor On hold
Papilio Plus/PacmanBuilding the Pacman implementation from http://fpgaarcade.com on the Spartan 6 hardware Completed
Papilio Plus/Fading counter A softly fading binary counter Completed
Papilio Plus/PS2 Keyboard Using the PS/2 keyboard interface Completed
Papilio Plus/SRAM test 2 writes and verifies test patterns in the SRAM on the Papilio Plus @ 100MHz Completed
CUGA-1 A CPU Using Gate Arrays On hold

There is also a whole lot of mini projects on the Papilio Plus page, for testing interfaces.

Unless any of the source files from this site contains headers that indicate otherwise (e.g.in 'CoreGen' components), all of this code is released under the BSD/MIT http://opensource.org/licenses/MIT - Feel free to do anything you want with it.

If you would like this disclaimer added to any particular file then please let me know and I will add it for you.

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