From Hamsterworks Wiki!
Welcome to the second part of the FPGA course!
Having problems with your code? Do I need to change something? Want a reference solution to the project? Email me at "email@example.com", after removing the "nospam-" bit. I'll try to get back to you in a day or so.
Aim of module
Getting the first design to work is always the hardest part.
This module will wire two switches up to two LEDs.
- Create a new project
- Create a new VHDL module
- Enter basic code
- Implement the design
- Create an implementation constraints file
- Implement the design again
- Use the hardware programming tool
- Test the design in hardware
- Build experience single wire inputs and outputs
Wow! That is a lot of learning for a second module
Step 1 - Create a new Project
- Click on "Xilinx ISE Design Suite 13.3" Studio Icon - From the "File" menu, choose "New Project" - Name the project "Switches+LEDs", and click on "Next".
- This screen is where you say what FPGA you are using. Choose the following settings to tell the design tools what chip you are using (if you are using the larger gate count FPGA then select xc3s250e), then press the "Next" button.
- Click on the "Finish" button to create and open the new project
Step 2 - Create a new VHDL Module
- Right-click on the design window, on the FPGA device, and choose "New Source"
(Must fix - screenshot is from an different project hence the wrong chip name)
- Highlight "VHDL module" and in the file name enter "Switches_LEDs", then press the "Next button". - This next dialog box allows you to define what connections the module has. We need four connections - two the the switches and two for the LEDs:
- Click the "Next" button, then "Finish" to create the module and open it in the editor. To make things clearer, delete any line that starts with "--" - they are comments that do not influence the design.
1: library IEEE; 2: use IEEE.STD_LOGIC_1164.ALL; 3: 4: entity Switches_LEDs is 5: Port ( switch_0 : in STD_LOGIC; 6: switch_1 : in STD_LOGIC; 7: LED_0 : out STD_LOGIC; 8: LED_1 : out STD_LOGIC); 9: end Switches_LEDs; 10: 11: architecture Behavioral of Switches_LEDs is 12: begin 13: 14: end Behavioral;
As you can see, it has created the definition for an entity called Switches_LEDs, with two inputs and two outputs - STD_LOGIC is used to indicate what values these inputs and outputs can have.
The architecture section is where you describe how the internal logic of the module actually works. For this project we use the "assignment" operator ("<=") to assign the LEDs the values of the switches:
1: library IEEE; 2: use IEEE.STD_LOGIC_1164.ALL; 3: 4: entity Switches_LEDs is 5: Port ( switch_0 : in STD_LOGIC; 6: switch_1 : in STD_LOGIC; 7: LED_0 : out STD_LOGIC; 8: LED_1 : out STD_LOGIC); 9: end Switches_LEDs; 10: 11: architecture Behavioral of Switches_LEDs is 12: begin 13: LED_0 <= switch_0; 14: LED_1 <= switch_1; 15: end Behavioral;
If you press the green "play" arrow in the middle left of the design window the project should start building.
If your code has been entered successfully the project will build without any errors, and the design Window will now look like this:
Great! You've built your first design! There is only one problem, and that is we haven't told the design tools which pin to connect these signals to.
Step 3 - Creating constraints
To tell the tools which pins to connect the signals to an "Implementation Constraints File" is needed.
- From the "Project Menu" choose "New Source"
- Select "Implemntation Constraints File" and call it "constraints":
- Click "Next" and "Finished".
- In the design windows, a small '+' will appear by the Switches_LEDs module. Click that to show the new file:
((Must fix - Once again FPGA is not showing the correct type)
- Double click "constraints.ucf" to open it in the editor window.
- Add the following lines, which assign locations to the four wires, and instructs the tools to create a design that uses "Low Voltage Transistor Transistor Logic" signal levels:
NET switch_1 LOC = "L3" | IOSTANDARD=LVTTL; NET switch_0 LOC = "P11" | IOSTANDARD=LVTTL; NET LED_1 LOC = "M11" | IOSTANDARD=LVTTL; NET LED_0 LOC = "M5" | IOSTANDARD=LVTTL;
If you are not using the BASYS2 board, check your documentation for which I/O pins are wired to the switches and LEDs - these constraints (and those in all the other modules) are only applicable to the BASYS2 board! Save the changes to this file, and then once again click on the Green arrow to build the design.
If that is successful, double click on "Generate Programming file":
You will now have a 'bit' file in the project directory that can be used to program the FPGA!
Step 4 - Downloading the design into the device
For the Basys2:
- Launch Digilent's Adept software
- If the device isn't automatically detected, click on the "Device manager" and add it to the device table.
- Use the browse button to search for your project's .bit file
- Press the program button, and ignore the warnings about the JTAG clock
- The design will be downloaded, and then the board will be configured with your design
Viewing how your design has been implemented
I find it interesting to see what the software tools make of my designs. If you are keen you are able to view how your design is implemented within the FPGA at three different levels - Register Transfer, Technology and the Routed Design.
You can find the options to view buried away in the process tree:
Here's a few screen shots from some other designs, and various different designs:
- The Register Transfer Level ('RTL') schematic, which shows how all your design-level components are connected:
- The Technology Schematic, which shows how the individual components within the FPGA are connected:
- The Routed Design, which shows the physical locations and interconnects that are used on the FPGA chip:
Ready to carry on?
Click here to carry on to the next module.