Module 2

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Getting the first design to work is always the hardest.

Contents

Aim of project

To wire two switches up to the LEDs.

Learning outcomes

  • Create a new project
  • Create a new VHDL module
  • Enter basic code
  • Implement the design
  • Create an implementation constraints file
  • Try the programming tools
  • Test the design in hardware
  • Experience single wire inputs and outputs

Wow! That is a lot of learning for a second module

Steps

Step 1 - New Project

- Click on "Xilinx ISE Design Suite 13.3" Studio Icon - From the "File" menu, choose "New Project" - Name the project "Switches+LEDs", and click on "Next".

M1p1.png

- This screen is where you say what FPGA you are using. Choose the following settings to tell the design tools what chip you are using, then press the "Next" button.

M1p2.png

- Click on the "Finish" button to create and open the new project

Step 2 - New VHDL Module

- Right-click on the design window, on the FPGA device, and choose "New Source"

M1p3.png

- Highlight "VHDL module" and in the file name enter "Switches_LEDs", then press the "Next button". - This next dialog box allows you to define what connections the module has. We need four connections - two the the switches and two for the LEDs:

M1p4.png

- Click the "Next" button, then "Finish" to create the module and open it in the editor:

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    21:56:05 12/15/2011 
-- Design Name: 
-- Module Name:    Switches_LEDs - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Switches_LEDs is
    Port ( switch_0 : in  STD_LOGIC;
           switch_1 : in  STD_LOGIC;
           LED_0 : out  STD_LOGIC;
           LED_1 : out  STD_LOGIC);
end Switches_LEDs;

architecture Behavioral of Switches_LEDs is

begin


end Behavioral;

To make things clearer, delete any line that starts with "--" - they are comments that do not influence the design.

 1: library IEEE;
 2: use IEEE.STD_LOGIC_1164.ALL;
 3:
 4: entity Switches_LEDs is
 5:    Port ( switch_0 : in  STD_LOGIC;
 6:           switch_1 : in  STD_LOGIC;
 7:           LED_0 : out  STD_LOGIC;
 8:           LED_1 : out  STD_LOGIC);
 9: end Switches_LEDs;
10:
11: architecture Behavioral of Switches_LEDs is
12: begin
13:
14: end Behavioral;

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