Module 20

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Please make sure that you have completed the earlier modules of FPGA course.

Having problems with your code? Do I need to change something? Want a reference solution to the project? Email me at "", after removing the "nospam-" bit. I'll try to get back to you in a day or so.


Aim of this module

  • Learn how tri state logic is implemented withing FPGAs
  • Learn how tri state logic is used when interfacing with an FPGA

What is tri state logic?

Put simply, tri-state logic is where a signal can be either "logic high level", "logic low level" or "not actively driven" - '1', '0' and 'Z' in VHDL. This allows the same wire / signal to be used as both an input or output, or allow multiple devices to share "share" a common bus.

The most familiar example is a RAM chip's data bus. During the read cycles the memory chip drives the data bus, and during write cycles the memory controller drives the data bus. To enable this most RAM chips have a signal called "Output Enable" ("OE") that tells the chip when to drive the bus.

On a tristate bus all devices on the bus can read the value of the bus at any time, but to avoid data corruption your design must ensure that one device should drive the bus at any time. Should two or more devices try to drive the bus to different values at the same time the data on the bus will be corrupted. If this overlap of multiple devices driving the bus lasts for only for a short time the error may not noticed, but you will get high power usage and signal integrity as the drivers are saturated.

How is tri-state logic used within a FPGA

In short, for the Spartan 3E it isn't. To avoid timing and power issues the design tools ensure that any signals are only ever driven by one device.

Any internal tri-state logic within a design is mapped into a hidden "input" and "output" signals. The bus is then implemented with a multiplexer that selects the active 'output' signal and then delivers that signal to all the inputs.

How is tri-state logic use when interfacing with a FPGA

Most general purpose I/O pins are of an FPGA are driven by a tri-state driver, and the pin is monitored by an input buffer.

When any internal tri-state is attached to an I/O pin it is implemented as three signals driving an IOBUF component:


  • 'T' controls the state of the tri-state driver
  • 'O' is the value of the pin
  • 'I' is the value that will be sent to the pin when 'T' is asserted.

(Yes, the signal names do seem the wrong way around, but they are from the IOBUFs point of view)

Project 20.1

  • Create a new project
  • Configure two of the PMOD pins. Remember to define the PMOD pins as "INOUT"!
  • Have 2 LEDs show the status to the two pins on a PMOD connector,
 led(0) <= pmod(0);
 led(1) <= pmod(1);
  • Connect two slide switches to these pins
   pmod(0) <= sw(0);
   pmod(1) <= sw(1);
  • Put a 300 Ohm + resistor between the two pins (to limit the current if both pins are driven at once)
  • Put a voltmeter across the resistor.
  • Play around with the design
    • What is the highest voltage you can over the resistor?
    • How much power is this ( remember P=V^2/R)
  • using a third slide switch decide which of the pins will be in high-Z mode. Something like:
   if sw(2) = '1' then 
     pmod(0) <= 'Z';
     pmod(1) <= sw(1);
     pmod(0) <= sw(0);
     pmod(1) <= 'Z';
   end if;
 end process;
  • Play around with it.
    • What is the highest voltage you can get over the resistor now?
    • How much power is this?

Ready to carry on?

Sorry! All finished! Apart from the advanced feature of the I/O blocks (such as DDR2 input and outputs) you've pretty much played with all the features of the Spartan 3E.

So if you are still keen to learn more:

  • have a read through the Xilinx AppNotes library. The ones on creative uses of BRAM and MULT18s is full of good ideas
  • read through full Spartan 3E User Guide - it will make some sense now.
  • create a system using the PicoBlaze embedded processor
  • sell or gift your Basys2 board to a friend and move up to a Nexys3 with off-chip RAM and ROM, or maybe an Atlys with HDMI and audio DACs/ADCs
  • try a different FPGA vendor's board - that will really make your head hurt
  • Have a go at building something really nifty

If there is something I've missed or you want to say thanks send me an email - or maybe send me postcard to me at 370 Ellesmere Junction Road, Springston 7616, Canterbury, New Zealand. It will be fun to see if I actually get any cards!

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