Synth beep

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This is part of my Synth project for FPGAs.

Contents

Making a noise

It is pretty simple to make a noise. All that is needed is to toggle the level of the audio output at a rate quick enough to be heard (between 20 and 20,000Hz).

As the clock on the Papilio One runs at 32,000,000 Hz all we need to do is divide this clock using a 16 bit counter. That will give a 488.3Hz tone.

Not very exciting, but more than enough to verify that the FPGA hardware is working correctly.

Source Code

Constraints file

# Constraints for the Papilio One 250 and LogicStart megawing
CONFIG PROHIBIT=P99;
CONFIG PROHIBIT=P43;
CONFIG PROHIBIT=P42;
CONFIG PROHIBIT=P39;
CONFIG PROHIBIT=P49;
CONFIG PROHIBIT=P48;
CONFIG PROHIBIT=P47;
CONFIG PART=XC3S250E-VQ100-4;

NET CLK32          LOC="P89"  | IOSTANDARD=LVCMOS25 | PERIOD=31.25ns;               
NET "clk32" TNM_NET = clk32;
TIMESPEC TS_clk32 = PERIOD "clk32" 32 MHz HIGH 50%;

NET AUDIO        LOC="P41";

synth.vhd

----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz<
-- 
-- Module Name:    synth - Behavioral 
--
-- Generate a beep
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity synth is
    Port ( clk32  : in  STD_LOGIC;
           audio  : out STD_LOGIC;
           switch : in  STD_LOGIC_VECTOR (7 downto 0));
end synth;

architecture Behavioral of synth is
   signal count         : unsigned  (15 downto 0) := (others => '0');
begin
   audio <= std_logic(count(15));
	
process(clk32)
   begin
      if rising_edge(clk32) then
         count <= count+1;
      end if;
   end process;
end Behavioral;

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